test-simulator-cond-rd-operand-rn-ror-amount-t32.cc revision ec4fdd22abecf1b8f52ee9dbff596ebdded9b5d6
1// Copyright 2016, VIXL authors 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are met: 6// 7// * Redistributions of source code must retain the above copyright notice, 8// this list of conditions and the following disclaimer. 9// * Redistributions in binary form must reproduce the above copyright notice, 10// this list of conditions and the following disclaimer in the documentation 11// and/or other materials provided with the distribution. 12// * Neither the name of ARM Limited nor the names of its contributors may be 13// used to endorse or promote products derived from this software without 14// specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 28// ----------------------------------------------------------------------------- 29// This file is auto generated from the 30// test/aarch32/config/template-simulator-aarch32.cc.in template file using 31// tools/generate_tests.py. 32// 33// PLEASE DO NOT EDIT. 34// ----------------------------------------------------------------------------- 35 36 37#include "test-runner.h" 38 39#include "test-utils.h" 40#include "test-utils-aarch32.h" 41 42#include "aarch32/assembler-aarch32.h" 43#include "aarch32/macro-assembler-aarch32.h" 44#include "aarch32/disasm-aarch32.h" 45 46#define __ masm. 47#define BUF_SIZE (4096) 48 49#ifdef VIXL_INCLUDE_SIMULATOR 50// Run tests with the simulator. 51 52#define SETUP() MacroAssembler masm(BUF_SIZE) 53 54#define START() masm.GetBuffer().Reset() 55 56#define END() \ 57 __ Hlt(0); \ 58 __ FinalizeCode(); 59 60// TODO: Run the tests in the simulator. 61#define RUN() 62 63#define TEARDOWN() 64 65#else // ifdef VIXL_INCLUDE_SIMULATOR. 66 67#define SETUP() MacroAssembler masm(BUF_SIZE); 68 69#define START() \ 70 masm.GetBuffer().Reset(); \ 71 __ Push(r4); \ 72 __ Push(r5); \ 73 __ Push(r6); \ 74 __ Push(r7); \ 75 __ Push(r8); \ 76 __ Push(r9); \ 77 __ Push(r10); \ 78 __ Push(r11); \ 79 __ Push(r12); \ 80 __ Push(lr) 81 82#define END() \ 83 __ Pop(lr); \ 84 __ Pop(r12); \ 85 __ Pop(r11); \ 86 __ Pop(r10); \ 87 __ Pop(r9); \ 88 __ Pop(r8); \ 89 __ Pop(r7); \ 90 __ Pop(r6); \ 91 __ Pop(r5); \ 92 __ Pop(r4); \ 93 __ Bx(lr); \ 94 __ FinalizeCode(); 95 96// Copy the generated code into a memory area garanteed to be executable before 97// executing it. 98#define RUN() \ 99 { \ 100 ExecutableMemory code(masm.GetBuffer().GetCursorOffset()); \ 101 code.Write(masm.GetBuffer().GetOffsetAddress<byte*>(0), \ 102 masm.GetBuffer().GetCursorOffset()); \ 103 int pcs_offset = masm.IsUsingT32() ? 1 : 0; \ 104 code.Execute(pcs_offset); \ 105 } 106 107#define TEARDOWN() 108 109#endif // ifdef VIXL_INCLUDE_SIMULATOR 110 111namespace vixl { 112namespace aarch32 { 113 114// List of instruction encodings: 115#define FOREACH_INSTRUCTION(M) \ 116 M(Sxtb) \ 117 M(Sxtb16) \ 118 M(Sxth) \ 119 M(Uxtb) \ 120 M(Uxtb16) \ 121 M(Uxth) 122 123 124// Values to be passed to the assembler to produce the instruction under test. 125struct Operands { 126 Condition cond; 127 Register rd; 128 Register rn; 129 ShiftType ror; 130 uint32_t amount; 131}; 132 133// Input data to feed to the instruction. 134struct Inputs { 135 uint32_t apsr; 136 uint32_t rd; 137 uint32_t rn; 138}; 139 140// This structure contains all input data needed to test one specific encoding. 141// It used to generate a loop over an instruction. 142struct TestLoopData { 143 // The `operands` fields represents the values to pass to the assembler to 144 // produce the instruction. 145 Operands operands; 146 // Description of the operands, used for error reporting. 147 const char* operands_description; 148 // Unique identifier, used for generating traces. 149 const char* identifier; 150 // Array of values to be fed to the instruction. 151 size_t input_size; 152 const Inputs* inputs; 153}; 154 155static const Inputs kCondition[] = {{NFlag, 0xabababab, 0xabababab}, 156 {ZFlag, 0xabababab, 0xabababab}, 157 {CFlag, 0xabababab, 0xabababab}, 158 {VFlag, 0xabababab, 0xabababab}, 159 {NZFlag, 0xabababab, 0xabababab}, 160 {NCFlag, 0xabababab, 0xabababab}, 161 {NVFlag, 0xabababab, 0xabababab}, 162 {ZCFlag, 0xabababab, 0xabababab}, 163 {ZVFlag, 0xabababab, 0xabababab}, 164 {CVFlag, 0xabababab, 0xabababab}, 165 {NZCFlag, 0xabababab, 0xabababab}, 166 {NZVFlag, 0xabababab, 0xabababab}, 167 {NCVFlag, 0xabababab, 0xabababab}, 168 {ZCVFlag, 0xabababab, 0xabababab}, 169 {NZCVFlag, 0xabababab, 0xabababab}}; 170 171static const Inputs kRdIsRn[] = {{NoFlag, 0x00000000, 0x00000000}, 172 {NoFlag, 0x00000001, 0x00000001}, 173 {NoFlag, 0x00000002, 0x00000002}, 174 {NoFlag, 0x00000020, 0x00000020}, 175 {NoFlag, 0x0000007d, 0x0000007d}, 176 {NoFlag, 0x0000007e, 0x0000007e}, 177 {NoFlag, 0x0000007f, 0x0000007f}, 178 {NoFlag, 0x00007ffd, 0x00007ffd}, 179 {NoFlag, 0x00007ffe, 0x00007ffe}, 180 {NoFlag, 0x00007fff, 0x00007fff}, 181 {NoFlag, 0x33333333, 0x33333333}, 182 {NoFlag, 0x55555555, 0x55555555}, 183 {NoFlag, 0x7ffffffd, 0x7ffffffd}, 184 {NoFlag, 0x7ffffffe, 0x7ffffffe}, 185 {NoFlag, 0x7fffffff, 0x7fffffff}, 186 {NoFlag, 0x80000000, 0x80000000}, 187 {NoFlag, 0x80000001, 0x80000001}, 188 {NoFlag, 0xaaaaaaaa, 0xaaaaaaaa}, 189 {NoFlag, 0xcccccccc, 0xcccccccc}, 190 {NoFlag, 0xffff8000, 0xffff8000}, 191 {NoFlag, 0xffff8001, 0xffff8001}, 192 {NoFlag, 0xffff8002, 0xffff8002}, 193 {NoFlag, 0xffff8003, 0xffff8003}, 194 {NoFlag, 0xffffff80, 0xffffff80}, 195 {NoFlag, 0xffffff81, 0xffffff81}, 196 {NoFlag, 0xffffff82, 0xffffff82}, 197 {NoFlag, 0xffffff83, 0xffffff83}, 198 {NoFlag, 0xffffffe0, 0xffffffe0}, 199 {NoFlag, 0xfffffffd, 0xfffffffd}, 200 {NoFlag, 0xfffffffe, 0xfffffffe}, 201 {NoFlag, 0xffffffff, 0xffffffff}}; 202 203static const Inputs kRdIsNotRn[] = {{NoFlag, 0x00000002, 0xcccccccc}, 204 {NoFlag, 0x7ffffffd, 0x00007ffe}, 205 {NoFlag, 0xffffff80, 0x00000020}, 206 {NoFlag, 0xaaaaaaaa, 0xaaaaaaaa}, 207 {NoFlag, 0x33333333, 0xffffff82}, 208 {NoFlag, 0xffff8001, 0x7ffffffe}, 209 {NoFlag, 0xfffffffd, 0x00007ffe}, 210 {NoFlag, 0xffffff80, 0x80000000}, 211 {NoFlag, 0x00000001, 0x33333333}, 212 {NoFlag, 0xcccccccc, 0x7ffffffe}, 213 {NoFlag, 0x00000000, 0xcccccccc}, 214 {NoFlag, 0x00000000, 0x55555555}, 215 {NoFlag, 0xffffffff, 0xffffffff}, 216 {NoFlag, 0x0000007e, 0xffff8002}, 217 {NoFlag, 0x80000000, 0x7ffffffd}, 218 {NoFlag, 0xffffff81, 0x0000007e}, 219 {NoFlag, 0x0000007f, 0xffff8001}, 220 {NoFlag, 0xffffffe0, 0x00007ffd}, 221 {NoFlag, 0xffff8003, 0x00000002}, 222 {NoFlag, 0xffffff83, 0x55555555}, 223 {NoFlag, 0xffffff83, 0xffffff80}, 224 {NoFlag, 0xffffff81, 0xffff8000}, 225 {NoFlag, 0x00000020, 0x7ffffffe}, 226 {NoFlag, 0xffffffe0, 0x00000000}, 227 {NoFlag, 0x7fffffff, 0x0000007e}, 228 {NoFlag, 0x80000001, 0xffffffff}, 229 {NoFlag, 0x00000001, 0x80000001}, 230 {NoFlag, 0x00000002, 0x0000007f}, 231 {NoFlag, 0x7fffffff, 0xcccccccc}, 232 {NoFlag, 0x80000001, 0x00007ffe}, 233 {NoFlag, 0xffff8002, 0x0000007e}, 234 {NoFlag, 0x00007ffe, 0xcccccccc}, 235 {NoFlag, 0x80000000, 0xffff8002}, 236 {NoFlag, 0xffffff83, 0x7ffffffe}, 237 {NoFlag, 0xffff8001, 0x00000001}, 238 {NoFlag, 0xffffff81, 0x00000020}, 239 {NoFlag, 0xfffffffe, 0xffff8001}, 240 {NoFlag, 0xffffffff, 0xfffffffe}, 241 {NoFlag, 0xcccccccc, 0x55555555}, 242 {NoFlag, 0x00000020, 0xffffff83}, 243 {NoFlag, 0xffffff83, 0xffff8001}, 244 {NoFlag, 0xffffff83, 0xffff8000}, 245 {NoFlag, 0x00007fff, 0x00000002}, 246 {NoFlag, 0x55555555, 0xffff8000}, 247 {NoFlag, 0x80000001, 0xffffff81}, 248 {NoFlag, 0x00000002, 0x00000000}, 249 {NoFlag, 0x33333333, 0xffffff81}, 250 {NoFlag, 0xffff8001, 0xffffff82}, 251 {NoFlag, 0xcccccccc, 0xffff8003}, 252 {NoFlag, 0xffff8003, 0x7ffffffd}, 253 {NoFlag, 0x0000007d, 0x00007ffe}, 254 {NoFlag, 0xffffff80, 0x0000007d}, 255 {NoFlag, 0xaaaaaaaa, 0x00007ffd}, 256 {NoFlag, 0x80000000, 0xffffff82}, 257 {NoFlag, 0x00000002, 0x7ffffffe}, 258 {NoFlag, 0x00000002, 0xffffff83}, 259 {NoFlag, 0x55555555, 0x00000002}, 260 {NoFlag, 0xffffffff, 0xffffff82}, 261 {NoFlag, 0xaaaaaaaa, 0x00000020}, 262 {NoFlag, 0x00000001, 0xffffff82}, 263 {NoFlag, 0x0000007f, 0xffffff82}, 264 {NoFlag, 0x7ffffffd, 0xaaaaaaaa}, 265 {NoFlag, 0x00007ffe, 0x00000001}, 266 {NoFlag, 0xfffffffd, 0xffffffe0}, 267 {NoFlag, 0xffffff81, 0xffffff83}, 268 {NoFlag, 0x0000007d, 0x00000000}, 269 {NoFlag, 0x0000007d, 0xffff8000}, 270 {NoFlag, 0xffffff81, 0x7fffffff}, 271 {NoFlag, 0xffffffff, 0x80000000}, 272 {NoFlag, 0x00000000, 0x00000001}, 273 {NoFlag, 0x55555555, 0xffffff82}, 274 {NoFlag, 0x00007ffe, 0x00007ffe}, 275 {NoFlag, 0x80000001, 0xfffffffd}, 276 {NoFlag, 0x00007fff, 0x33333333}, 277 {NoFlag, 0x00007fff, 0x80000000}, 278 {NoFlag, 0xcccccccc, 0x00007fff}, 279 {NoFlag, 0xfffffffe, 0xffffffe0}, 280 {NoFlag, 0x7ffffffe, 0x0000007f}, 281 {NoFlag, 0x00007ffd, 0xffff8001}, 282 {NoFlag, 0x00000002, 0x00000001}, 283 {NoFlag, 0x80000000, 0xffffffff}, 284 {NoFlag, 0xffffff83, 0xcccccccc}, 285 {NoFlag, 0xffff8002, 0x7ffffffe}, 286 {NoFlag, 0xaaaaaaaa, 0x00000000}, 287 {NoFlag, 0xffffff80, 0xcccccccc}, 288 {NoFlag, 0x33333333, 0xffffff83}, 289 {NoFlag, 0x0000007e, 0xffffffe0}, 290 {NoFlag, 0x0000007e, 0x00007fff}, 291 {NoFlag, 0x0000007f, 0x00000002}, 292 {NoFlag, 0x7ffffffe, 0xcccccccc}, 293 {NoFlag, 0x0000007d, 0xffffff80}, 294 {NoFlag, 0x00007fff, 0x00000020}, 295 {NoFlag, 0x7ffffffe, 0xfffffffe}, 296 {NoFlag, 0xfffffffe, 0xffffff81}, 297 {NoFlag, 0xffffffff, 0x0000007f}, 298 {NoFlag, 0xffff8002, 0x7ffffffd}, 299 {NoFlag, 0xffff8001, 0xfffffffe}, 300 {NoFlag, 0x33333333, 0xffff8002}, 301 {NoFlag, 0x00000000, 0xffffffff}, 302 {NoFlag, 0x33333333, 0xffffff80}, 303 {NoFlag, 0x0000007f, 0x00007fff}, 304 {NoFlag, 0xffffffff, 0xffff8001}, 305 {NoFlag, 0x7fffffff, 0xffff8002}, 306 {NoFlag, 0x7ffffffd, 0xffffff83}, 307 {NoFlag, 0x7fffffff, 0x0000007f}, 308 {NoFlag, 0xffffff83, 0xfffffffe}, 309 {NoFlag, 0x7ffffffe, 0xffff8003}, 310 {NoFlag, 0xffff8002, 0xffff8002}, 311 {NoFlag, 0x80000001, 0x0000007f}, 312 {NoFlag, 0x00000020, 0x00000002}, 313 {NoFlag, 0xffffff82, 0xffff8001}, 314 {NoFlag, 0xffffffff, 0x00000001}, 315 {NoFlag, 0xffffff80, 0xffff8002}, 316 {NoFlag, 0xffff8003, 0x7fffffff}, 317 {NoFlag, 0xffffffff, 0xffff8000}, 318 {NoFlag, 0xffff8002, 0x00007ffd}, 319 {NoFlag, 0x00000020, 0xffffff81}, 320 {NoFlag, 0x00000001, 0x55555555}, 321 {NoFlag, 0x7ffffffe, 0x00000020}, 322 {NoFlag, 0x80000000, 0x00000001}, 323 {NoFlag, 0x00007ffd, 0xffff8002}, 324 {NoFlag, 0x7fffffff, 0xfffffffe}, 325 {NoFlag, 0xcccccccc, 0x00007ffd}, 326 {NoFlag, 0x00000000, 0xfffffffd}, 327 {NoFlag, 0xffff8003, 0xffffff80}, 328 {NoFlag, 0x80000001, 0xffffff80}, 329 {NoFlag, 0xffffffff, 0xffff8002}, 330 {NoFlag, 0x00007ffe, 0xffff8002}, 331 {NoFlag, 0xffffff80, 0x00007ffe}, 332 {NoFlag, 0x80000001, 0xffff8001}, 333 {NoFlag, 0x0000007f, 0xffffff80}, 334 {NoFlag, 0xffffff81, 0x80000000}, 335 {NoFlag, 0x00007fff, 0x00007ffe}, 336 {NoFlag, 0x33333333, 0xffff8000}, 337 {NoFlag, 0x33333333, 0x00007fff}, 338 {NoFlag, 0x00000000, 0x0000007d}, 339 {NoFlag, 0x80000001, 0x00000000}, 340 {NoFlag, 0xffffffff, 0x55555555}, 341 {NoFlag, 0x80000001, 0x80000000}, 342 {NoFlag, 0xffffffff, 0xffffff80}, 343 {NoFlag, 0xffffff81, 0xffff8003}, 344 {NoFlag, 0x55555555, 0x80000001}, 345 {NoFlag, 0x7fffffff, 0xffff8001}, 346 {NoFlag, 0xffffff83, 0x00000002}, 347 {NoFlag, 0x0000007e, 0xffffff81}, 348 {NoFlag, 0x80000000, 0xffff8001}, 349 {NoFlag, 0xffffff80, 0xfffffffe}, 350 {NoFlag, 0x0000007e, 0xfffffffd}, 351 {NoFlag, 0xffffffe0, 0xffffffff}, 352 {NoFlag, 0x55555555, 0x80000000}, 353 {NoFlag, 0x0000007d, 0x80000001}, 354 {NoFlag, 0xffffffe0, 0x7ffffffd}, 355 {NoFlag, 0x00000000, 0x00000000}, 356 {NoFlag, 0x55555555, 0x00000001}, 357 {NoFlag, 0x00007ffd, 0x7fffffff}, 358 {NoFlag, 0x55555555, 0xffffffff}, 359 {NoFlag, 0xffff8003, 0x00007fff}, 360 {NoFlag, 0xffffff82, 0x00007fff}, 361 {NoFlag, 0x33333333, 0x55555555}, 362 {NoFlag, 0x00000020, 0x33333333}, 363 {NoFlag, 0x7ffffffe, 0xfffffffd}, 364 {NoFlag, 0x7ffffffe, 0x00000001}, 365 {NoFlag, 0xffffff83, 0xffffffe0}, 366 {NoFlag, 0xfffffffe, 0xaaaaaaaa}, 367 {NoFlag, 0xffff8002, 0x33333333}, 368 {NoFlag, 0xffff8002, 0xffff8003}, 369 {NoFlag, 0x33333333, 0x7fffffff}, 370 {NoFlag, 0xfffffffd, 0xffffff83}, 371 {NoFlag, 0x00000000, 0xffff8000}, 372 {NoFlag, 0xffffff82, 0x55555555}, 373 {NoFlag, 0xffffff82, 0xffffff81}, 374 {NoFlag, 0xcccccccc, 0xfffffffe}, 375 {NoFlag, 0xfffffffd, 0x7fffffff}, 376 {NoFlag, 0x00007fff, 0x7fffffff}, 377 {NoFlag, 0xffffff83, 0xffff8003}, 378 {NoFlag, 0xfffffffe, 0xffffffff}, 379 {NoFlag, 0x7ffffffd, 0x00007ffd}, 380 {NoFlag, 0x7ffffffd, 0x00007fff}, 381 {NoFlag, 0x00007ffd, 0xffffffff}, 382 {NoFlag, 0x00000001, 0xffff8003}, 383 {NoFlag, 0xffffff80, 0xfffffffd}, 384 {NoFlag, 0x33333333, 0x80000000}, 385 {NoFlag, 0xffff8001, 0x00000020}, 386 {NoFlag, 0xcccccccc, 0x00000002}, 387 {NoFlag, 0x00000000, 0x00000002}, 388 {NoFlag, 0x0000007d, 0x00007fff}, 389 {NoFlag, 0xcccccccc, 0x00000001}, 390 {NoFlag, 0xffffff83, 0x00007fff}, 391 {NoFlag, 0x80000001, 0x00000020}, 392 {NoFlag, 0xffff8003, 0xffffffe0}, 393 {NoFlag, 0x00007ffd, 0xaaaaaaaa}, 394 {NoFlag, 0x33333333, 0xffff8001}, 395 {NoFlag, 0xffffff83, 0x80000001}, 396 {NoFlag, 0xffff8000, 0xffff8000}, 397 {NoFlag, 0x00007ffe, 0xffff8001}, 398 {NoFlag, 0x7ffffffd, 0x00000000}, 399 {NoFlag, 0x00007ffe, 0x33333333}, 400 {NoFlag, 0xffff8001, 0xffffff80}, 401 {NoFlag, 0xfffffffe, 0x55555555}, 402 {NoFlag, 0xffffff82, 0xffffffff}}; 403 404static const Inputs kRotations[] = {{NoFlag, 0xabababab, 0x00000000}, 405 {NoFlag, 0xabababab, 0x00000001}, 406 {NoFlag, 0xabababab, 0x00000002}, 407 {NoFlag, 0xabababab, 0x00000020}, 408 {NoFlag, 0xabababab, 0x0000007d}, 409 {NoFlag, 0xabababab, 0x0000007e}, 410 {NoFlag, 0xabababab, 0x0000007f}, 411 {NoFlag, 0xabababab, 0x00007ffd}, 412 {NoFlag, 0xabababab, 0x00007ffe}, 413 {NoFlag, 0xabababab, 0x00007fff}, 414 {NoFlag, 0xabababab, 0x33333333}, 415 {NoFlag, 0xabababab, 0x55555555}, 416 {NoFlag, 0xabababab, 0x7ffffffd}, 417 {NoFlag, 0xabababab, 0x7ffffffe}, 418 {NoFlag, 0xabababab, 0x7fffffff}, 419 {NoFlag, 0xabababab, 0x80000000}, 420 {NoFlag, 0xabababab, 0x80000001}, 421 {NoFlag, 0xabababab, 0xaaaaaaaa}, 422 {NoFlag, 0xabababab, 0xcccccccc}, 423 {NoFlag, 0xabababab, 0xffff8000}, 424 {NoFlag, 0xabababab, 0xffff8001}, 425 {NoFlag, 0xabababab, 0xffff8002}, 426 {NoFlag, 0xabababab, 0xffff8003}, 427 {NoFlag, 0xabababab, 0xffffff80}, 428 {NoFlag, 0xabababab, 0xffffff81}, 429 {NoFlag, 0xabababab, 0xffffff82}, 430 {NoFlag, 0xabababab, 0xffffff83}, 431 {NoFlag, 0xabababab, 0xffffffe0}, 432 {NoFlag, 0xabababab, 0xfffffffd}, 433 {NoFlag, 0xabababab, 0xfffffffe}, 434 {NoFlag, 0xabababab, 0xffffffff}}; 435 436 437// A loop will be generated for each element of this array. 438static const TestLoopData kTests[] = {{{eq, r0, r0, ROR, 0}, 439 "eq r0 r0 ROR 0", 440 "Condition_eq_r0_r0_ROR_0", 441 ARRAY_SIZE(kCondition), 442 kCondition}, 443 {{ne, r0, r0, ROR, 0}, 444 "ne r0 r0 ROR 0", 445 "Condition_ne_r0_r0_ROR_0", 446 ARRAY_SIZE(kCondition), 447 kCondition}, 448 {{cs, r0, r0, ROR, 0}, 449 "cs r0 r0 ROR 0", 450 "Condition_cs_r0_r0_ROR_0", 451 ARRAY_SIZE(kCondition), 452 kCondition}, 453 {{cc, r0, r0, ROR, 0}, 454 "cc r0 r0 ROR 0", 455 "Condition_cc_r0_r0_ROR_0", 456 ARRAY_SIZE(kCondition), 457 kCondition}, 458 {{mi, r0, r0, ROR, 0}, 459 "mi r0 r0 ROR 0", 460 "Condition_mi_r0_r0_ROR_0", 461 ARRAY_SIZE(kCondition), 462 kCondition}, 463 {{pl, r0, r0, ROR, 0}, 464 "pl r0 r0 ROR 0", 465 "Condition_pl_r0_r0_ROR_0", 466 ARRAY_SIZE(kCondition), 467 kCondition}, 468 {{vs, r0, r0, ROR, 0}, 469 "vs r0 r0 ROR 0", 470 "Condition_vs_r0_r0_ROR_0", 471 ARRAY_SIZE(kCondition), 472 kCondition}, 473 {{vc, r0, r0, ROR, 0}, 474 "vc r0 r0 ROR 0", 475 "Condition_vc_r0_r0_ROR_0", 476 ARRAY_SIZE(kCondition), 477 kCondition}, 478 {{hi, r0, r0, ROR, 0}, 479 "hi r0 r0 ROR 0", 480 "Condition_hi_r0_r0_ROR_0", 481 ARRAY_SIZE(kCondition), 482 kCondition}, 483 {{ls, r0, r0, ROR, 0}, 484 "ls r0 r0 ROR 0", 485 "Condition_ls_r0_r0_ROR_0", 486 ARRAY_SIZE(kCondition), 487 kCondition}, 488 {{ge, r0, r0, ROR, 0}, 489 "ge r0 r0 ROR 0", 490 "Condition_ge_r0_r0_ROR_0", 491 ARRAY_SIZE(kCondition), 492 kCondition}, 493 {{lt, r0, r0, ROR, 0}, 494 "lt r0 r0 ROR 0", 495 "Condition_lt_r0_r0_ROR_0", 496 ARRAY_SIZE(kCondition), 497 kCondition}, 498 {{gt, r0, r0, ROR, 0}, 499 "gt r0 r0 ROR 0", 500 "Condition_gt_r0_r0_ROR_0", 501 ARRAY_SIZE(kCondition), 502 kCondition}, 503 {{le, r0, r0, ROR, 0}, 504 "le r0 r0 ROR 0", 505 "Condition_le_r0_r0_ROR_0", 506 ARRAY_SIZE(kCondition), 507 kCondition}, 508 {{al, r0, r0, ROR, 0}, 509 "al r0 r0 ROR 0", 510 "Condition_al_r0_r0_ROR_0", 511 ARRAY_SIZE(kCondition), 512 kCondition}, 513 {{al, r0, r0, ROR, 0}, 514 "al r0 r0 ROR 0", 515 "RdIsRn_al_r0_r0_ROR_0", 516 ARRAY_SIZE(kRdIsRn), 517 kRdIsRn}, 518 {{al, r1, r1, ROR, 0}, 519 "al r1 r1 ROR 0", 520 "RdIsRn_al_r1_r1_ROR_0", 521 ARRAY_SIZE(kRdIsRn), 522 kRdIsRn}, 523 {{al, r2, r2, ROR, 0}, 524 "al r2 r2 ROR 0", 525 "RdIsRn_al_r2_r2_ROR_0", 526 ARRAY_SIZE(kRdIsRn), 527 kRdIsRn}, 528 {{al, r3, r3, ROR, 0}, 529 "al r3 r3 ROR 0", 530 "RdIsRn_al_r3_r3_ROR_0", 531 ARRAY_SIZE(kRdIsRn), 532 kRdIsRn}, 533 {{al, r4, r4, ROR, 0}, 534 "al r4 r4 ROR 0", 535 "RdIsRn_al_r4_r4_ROR_0", 536 ARRAY_SIZE(kRdIsRn), 537 kRdIsRn}, 538 {{al, r5, r5, ROR, 0}, 539 "al r5 r5 ROR 0", 540 "RdIsRn_al_r5_r5_ROR_0", 541 ARRAY_SIZE(kRdIsRn), 542 kRdIsRn}, 543 {{al, r6, r6, ROR, 0}, 544 "al r6 r6 ROR 0", 545 "RdIsRn_al_r6_r6_ROR_0", 546 ARRAY_SIZE(kRdIsRn), 547 kRdIsRn}, 548 {{al, r7, r7, ROR, 0}, 549 "al r7 r7 ROR 0", 550 "RdIsRn_al_r7_r7_ROR_0", 551 ARRAY_SIZE(kRdIsRn), 552 kRdIsRn}, 553 {{al, r8, r8, ROR, 0}, 554 "al r8 r8 ROR 0", 555 "RdIsRn_al_r8_r8_ROR_0", 556 ARRAY_SIZE(kRdIsRn), 557 kRdIsRn}, 558 {{al, r9, r9, ROR, 0}, 559 "al r9 r9 ROR 0", 560 "RdIsRn_al_r9_r9_ROR_0", 561 ARRAY_SIZE(kRdIsRn), 562 kRdIsRn}, 563 {{al, r10, r10, ROR, 0}, 564 "al r10 r10 ROR 0", 565 "RdIsRn_al_r10_r10_ROR_0", 566 ARRAY_SIZE(kRdIsRn), 567 kRdIsRn}, 568 {{al, r11, r11, ROR, 0}, 569 "al r11 r11 ROR 0", 570 "RdIsRn_al_r11_r11_ROR_0", 571 ARRAY_SIZE(kRdIsRn), 572 kRdIsRn}, 573 {{al, r12, r12, ROR, 0}, 574 "al r12 r12 ROR 0", 575 "RdIsRn_al_r12_r12_ROR_0", 576 ARRAY_SIZE(kRdIsRn), 577 kRdIsRn}, 578 {{al, r14, r14, ROR, 0}, 579 "al r14 r14 ROR 0", 580 "RdIsRn_al_r14_r14_ROR_0", 581 ARRAY_SIZE(kRdIsRn), 582 kRdIsRn}, 583 {{al, r1, r8, ROR, 0}, 584 "al r1 r8 ROR 0", 585 "RdIsNotRn_al_r1_r8_ROR_0", 586 ARRAY_SIZE(kRdIsNotRn), 587 kRdIsNotRn}, 588 {{al, r7, r4, ROR, 0}, 589 "al r7 r4 ROR 0", 590 "RdIsNotRn_al_r7_r4_ROR_0", 591 ARRAY_SIZE(kRdIsNotRn), 592 kRdIsNotRn}, 593 {{al, r14, r10, ROR, 0}, 594 "al r14 r10 ROR 0", 595 "RdIsNotRn_al_r14_r10_ROR_0", 596 ARRAY_SIZE(kRdIsNotRn), 597 kRdIsNotRn}, 598 {{al, r10, r6, ROR, 0}, 599 "al r10 r6 ROR 0", 600 "RdIsNotRn_al_r10_r6_ROR_0", 601 ARRAY_SIZE(kRdIsNotRn), 602 kRdIsNotRn}, 603 {{al, r6, r5, ROR, 0}, 604 "al r6 r5 ROR 0", 605 "RdIsNotRn_al_r6_r5_ROR_0", 606 ARRAY_SIZE(kRdIsNotRn), 607 kRdIsNotRn}, 608 {{al, r12, r2, ROR, 0}, 609 "al r12 r2 ROR 0", 610 "RdIsNotRn_al_r12_r2_ROR_0", 611 ARRAY_SIZE(kRdIsNotRn), 612 kRdIsNotRn}, 613 {{al, r0, r11, ROR, 0}, 614 "al r0 r11 ROR 0", 615 "RdIsNotRn_al_r0_r11_ROR_0", 616 ARRAY_SIZE(kRdIsNotRn), 617 kRdIsNotRn}, 618 {{al, r10, r14, ROR, 0}, 619 "al r10 r14 ROR 0", 620 "RdIsNotRn_al_r10_r14_ROR_0", 621 ARRAY_SIZE(kRdIsNotRn), 622 kRdIsNotRn}, 623 {{al, r0, r5, ROR, 0}, 624 "al r0 r5 ROR 0", 625 "RdIsNotRn_al_r0_r5_ROR_0", 626 ARRAY_SIZE(kRdIsNotRn), 627 kRdIsNotRn}, 628 {{al, r0, r3, ROR, 0}, 629 "al r0 r3 ROR 0", 630 "RdIsNotRn_al_r0_r3_ROR_0", 631 ARRAY_SIZE(kRdIsNotRn), 632 kRdIsNotRn}, 633 {{al, r0, r1, ROR, 0}, 634 "al r0 r1 ROR 0", 635 "Rotations_al_r0_r1_ROR_0", 636 ARRAY_SIZE(kRotations), 637 kRotations}, 638 {{al, r0, r1, ROR, 8}, 639 "al r0 r1 ROR 8", 640 "Rotations_al_r0_r1_ROR_8", 641 ARRAY_SIZE(kRotations), 642 kRotations}, 643 {{al, r0, r1, ROR, 16}, 644 "al r0 r1 ROR 16", 645 "Rotations_al_r0_r1_ROR_16", 646 ARRAY_SIZE(kRotations), 647 kRotations}, 648 {{al, r0, r1, ROR, 24}, 649 "al r0 r1 ROR 24", 650 "Rotations_al_r0_r1_ROR_24", 651 ARRAY_SIZE(kRotations), 652 kRotations}}; 653 654// We record all inputs to the instructions as outputs. This way, we also check 655// that what shouldn't change didn't change. 656struct TestResult { 657 size_t output_size; 658 const Inputs* outputs; 659}; 660 661// These headers each contain an array of `TestResult` with the reference output 662// values. The reference arrays are names `kReference{mnemonic}`. 663#include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxtb.h" 664#include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxtb16.h" 665#include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-sxth.h" 666#include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxtb.h" 667#include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxtb16.h" 668#include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-t32-uxth.h" 669 670 671// The maximum number of errors to report in detail for each test. 672static const unsigned kErrorReportLimit = 8; 673 674typedef void (MacroAssembler::*Fn)(Condition cond, 675 Register rd, 676 const Operand& op); 677 678static void TestHelper(Fn instruction, 679 const char* mnemonic, 680 const TestResult reference[]) { 681 SETUP(); 682 masm.UseT32(); 683 START(); 684 685 // Data to compare to `reference`. 686 TestResult* results[ARRAY_SIZE(kTests)]; 687 688 // Test cases for memory bound instructions may allocate a buffer and save its 689 // address in this array. 690 byte* scratch_memory_buffers[ARRAY_SIZE(kTests)]; 691 692 // Generate a loop for each element in `kTests`. Each loop tests one specific 693 // instruction. 694 for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) { 695 // Allocate results on the heap for this test. 696 results[i] = new TestResult; 697 results[i]->outputs = new Inputs[kTests[i].input_size]; 698 results[i]->output_size = kTests[i].input_size; 699 700 uintptr_t input_address = reinterpret_cast<uintptr_t>(kTests[i].inputs); 701 uintptr_t result_address = reinterpret_cast<uintptr_t>(results[i]->outputs); 702 703 scratch_memory_buffers[i] = NULL; 704 705 Label loop; 706 UseScratchRegisterScope scratch_registers(&masm); 707 // Include all registers from r0 ro r12. 708 scratch_registers.Include(RegisterList(0x1fff)); 709 710 // Values to pass to the macro-assembler. 711 Condition cond = kTests[i].operands.cond; 712 Register rd = kTests[i].operands.rd; 713 Register rn = kTests[i].operands.rn; 714 ShiftType ror = kTests[i].operands.ror; 715 uint32_t amount = kTests[i].operands.amount; 716 Operand op(rn, ror, amount); 717 scratch_registers.Exclude(rd); 718 scratch_registers.Exclude(rn); 719 720 // Allocate reserved registers for our own use. 721 Register input_ptr = scratch_registers.Acquire(); 722 Register input_end = scratch_registers.Acquire(); 723 Register result_ptr = scratch_registers.Acquire(); 724 725 // Initialize `input_ptr` to the first element and `input_end` the address 726 // after the array. 727 __ Mov(input_ptr, input_address); 728 __ Add(input_end, 729 input_ptr, 730 sizeof(kTests[i].inputs[0]) * kTests[i].input_size); 731 __ Mov(result_ptr, result_address); 732 __ Bind(&loop); 733 734 { 735 UseScratchRegisterScope temp_registers(&masm); 736 Register nzcv_bits = temp_registers.Acquire(); 737 Register saved_q_bit = temp_registers.Acquire(); 738 // Save the `Q` bit flag. 739 __ Mrs(saved_q_bit, APSR); 740 __ And(saved_q_bit, saved_q_bit, QFlag); 741 // Set the `NZCV` and `Q` flags together. 742 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr))); 743 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); 744 __ Msr(APSR_nzcvq, nzcv_bits); 745 } 746 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd))); 747 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn))); 748 749 (masm.*instruction)(cond, rd, op); 750 751 { 752 UseScratchRegisterScope temp_registers(&masm); 753 Register nzcv_bits = temp_registers.Acquire(); 754 __ Mrs(nzcv_bits, APSR); 755 // Only record the NZCV bits. 756 __ And(nzcv_bits, nzcv_bits, NZCVFlag); 757 __ Str(nzcv_bits, MemOperand(result_ptr, offsetof(Inputs, apsr))); 758 } 759 __ Str(rd, MemOperand(result_ptr, offsetof(Inputs, rd))); 760 __ Str(rn, MemOperand(result_ptr, offsetof(Inputs, rn))); 761 762 // Advance the result pointer. 763 __ Add(result_ptr, result_ptr, sizeof(kTests[i].inputs[0])); 764 // Loop back until `input_ptr` is lower than `input_base`. 765 __ Add(input_ptr, input_ptr, sizeof(kTests[i].inputs[0])); 766 __ Cmp(input_ptr, input_end); 767 __ B(ne, &loop); 768 } 769 770 END(); 771 772 RUN(); 773 774 if (Test::generate_test_trace()) { 775 // Print the results. 776 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 777 printf("static const Inputs kOutputs_%s_%s[] = {\n", 778 mnemonic, 779 kTests[i].identifier); 780 for (size_t j = 0; j < results[i]->output_size; j++) { 781 printf(" { "); 782 printf("0x%08" PRIx32, results[i]->outputs[j].apsr); 783 printf(", "); 784 printf("0x%08" PRIx32, results[i]->outputs[j].rd); 785 printf(", "); 786 printf("0x%08" PRIx32, results[i]->outputs[j].rn); 787 printf(" },\n"); 788 } 789 printf("};\n"); 790 } 791 printf("static const TestResult kReference%s[] = {\n", mnemonic); 792 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 793 printf(" {\n"); 794 printf(" ARRAY_SIZE(kOutputs_%s_%s),\n", 795 mnemonic, 796 kTests[i].identifier); 797 printf(" kOutputs_%s_%s,\n", mnemonic, kTests[i].identifier); 798 printf(" },\n"); 799 } 800 printf("};\n"); 801 } else if (kCheckSimulatorTestResults) { 802 // Check the results. 803 unsigned total_error_count = 0; 804 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 805 bool instruction_has_errors = false; 806 for (size_t j = 0; j < kTests[i].input_size; j++) { 807 uint32_t apsr = results[i]->outputs[j].apsr; 808 uint32_t rd = results[i]->outputs[j].rd; 809 uint32_t rn = results[i]->outputs[j].rn; 810 uint32_t apsr_input = kTests[i].inputs[j].apsr; 811 uint32_t rd_input = kTests[i].inputs[j].rd; 812 uint32_t rn_input = kTests[i].inputs[j].rn; 813 uint32_t apsr_ref = reference[i].outputs[j].apsr; 814 uint32_t rd_ref = reference[i].outputs[j].rd; 815 uint32_t rn_ref = reference[i].outputs[j].rn; 816 817 if (((apsr != apsr_ref) || (rd != rd_ref) || (rn != rn_ref)) && 818 (++total_error_count <= kErrorReportLimit)) { 819 // Print the instruction once even if it triggered multiple failures. 820 if (!instruction_has_errors) { 821 printf("Error(s) when testing \"%s %s\":\n", 822 mnemonic, 823 kTests[i].operands_description); 824 instruction_has_errors = true; 825 } 826 // Print subsequent errors. 827 printf(" Input: "); 828 printf("0x%08" PRIx32, apsr_input); 829 printf(", "); 830 printf("0x%08" PRIx32, rd_input); 831 printf(", "); 832 printf("0x%08" PRIx32, rn_input); 833 printf("\n"); 834 printf(" Expected: "); 835 printf("0x%08" PRIx32, apsr_ref); 836 printf(", "); 837 printf("0x%08" PRIx32, rd_ref); 838 printf(", "); 839 printf("0x%08" PRIx32, rn_ref); 840 printf("\n"); 841 printf(" Found: "); 842 printf("0x%08" PRIx32, apsr); 843 printf(", "); 844 printf("0x%08" PRIx32, rd); 845 printf(", "); 846 printf("0x%08" PRIx32, rn); 847 printf("\n\n"); 848 } 849 } 850 } 851 852 if (total_error_count > kErrorReportLimit) { 853 printf("%u other errors follow.\n", 854 total_error_count - kErrorReportLimit); 855 } 856 VIXL_CHECK(total_error_count == 0); 857 } else { 858 VIXL_WARNING("Assembled the code, but did not run anything.\n"); 859 } 860 861 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 862 delete[] results[i]->outputs; 863 delete results[i]; 864 delete[] scratch_memory_buffers[i]; 865 } 866 867 TEARDOWN(); 868} 869 870// Instantiate tests for each instruction in the list. 871#define TEST(mnemonic) \ 872 static void Test_##mnemonic() { \ 873 TestHelper(&MacroAssembler::mnemonic, #mnemonic, kReference##mnemonic); \ 874 } \ 875 static Test test_##mnemonic( \ 876 "AARCH32_SIMULATOR_COND_RD_OPERAND_RN_ROR_AMOUNT_T32_" #mnemonic, \ 877 &Test_##mnemonic); 878FOREACH_INSTRUCTION(TEST) 879#undef TEST 880 881} // aarch32 882} // vixl 883