test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc revision 6a049f97861bd71c69d81f643e42308d28c5de31
1// Copyright 2016, VIXL authors 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are met: 6// 7// * Redistributions of source code must retain the above copyright notice, 8// this list of conditions and the following disclaimer. 9// * Redistributions in binary form must reproduce the above copyright notice, 10// this list of conditions and the following disclaimer in the documentation 11// and/or other materials provided with the distribution. 12// * Neither the name of ARM Limited nor the names of its contributors may be 13// used to endorse or promote products derived from this software without 14// specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 28// ----------------------------------------------------------------------------- 29// This file is auto generated from the 30// test/aarch32/config/template-simulator-aarch32.cc.in template file using 31// tools/generate_tests.py. 32// 33// PLEASE DO NOT EDIT. 34// ----------------------------------------------------------------------------- 35 36 37#include "test-runner.h" 38 39#include "test-utils.h" 40#include "test-utils-aarch32.h" 41 42#include "aarch32/assembler-aarch32.h" 43#include "aarch32/macro-assembler-aarch32.h" 44#include "aarch32/disasm-aarch32.h" 45 46#define __ masm. 47#define BUF_SIZE (4096) 48 49#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32 50// Run tests with the simulator. 51 52#define SETUP() MacroAssembler masm(BUF_SIZE) 53 54#define START() masm.GetBuffer()->Reset() 55 56#define END() \ 57 __ Hlt(0); \ 58 __ FinalizeCode(); 59 60// TODO: Run the tests in the simulator. 61#define RUN() 62 63#define TEARDOWN() 64 65#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32. 66 67#define SETUP() MacroAssembler masm(BUF_SIZE); 68 69#define START() \ 70 masm.GetBuffer()->Reset(); \ 71 __ Push(r4); \ 72 __ Push(r5); \ 73 __ Push(r6); \ 74 __ Push(r7); \ 75 __ Push(r8); \ 76 __ Push(r9); \ 77 __ Push(r10); \ 78 __ Push(r11); \ 79 __ Push(r12); \ 80 __ Push(lr) 81 82#define END() \ 83 __ Pop(lr); \ 84 __ Pop(r12); \ 85 __ Pop(r11); \ 86 __ Pop(r10); \ 87 __ Pop(r9); \ 88 __ Pop(r8); \ 89 __ Pop(r7); \ 90 __ Pop(r6); \ 91 __ Pop(r5); \ 92 __ Pop(r4); \ 93 __ Bx(lr); \ 94 __ FinalizeCode(); 95 96#define RUN() \ 97 { \ 98 int pcs_offset = masm.IsUsingT32() ? 1 : 0; \ 99 masm.GetBuffer()->SetExecutable(); \ 100 ExecuteMemory(masm.GetBuffer()->GetStartAddress<byte*>(), \ 101 masm.GetSizeOfCodeGenerated(), \ 102 pcs_offset); \ 103 masm.GetBuffer()->SetWritable(); \ 104 } 105 106#define TEARDOWN() 107 108#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32 109 110namespace vixl { 111namespace aarch32 { 112 113// List of instruction encodings: 114#define FOREACH_INSTRUCTION(M) \ 115 M(Cmn) \ 116 M(Cmp) \ 117 M(Mov) \ 118 M(Movs) \ 119 M(Mvn) \ 120 M(Mvns) \ 121 M(Teq) \ 122 M(Tst) 123 124 125// Values to be passed to the assembler to produce the instruction under test. 126struct Operands { 127 Condition cond; 128 Register rd; 129 Register rn; 130 ShiftType shift; 131 uint32_t amount; 132}; 133 134// Input data to feed to the instruction. 135struct Inputs { 136 uint32_t apsr; 137 uint32_t rd; 138 uint32_t rn; 139}; 140 141// This structure contains all input data needed to test one specific encoding. 142// It used to generate a loop over an instruction. 143struct TestLoopData { 144 // The `operands` fields represents the values to pass to the assembler to 145 // produce the instruction. 146 Operands operands; 147 // Description of the operands, used for error reporting. 148 const char* operands_description; 149 // Unique identifier, used for generating traces. 150 const char* identifier; 151 // Array of values to be fed to the instruction. 152 size_t input_size; 153 const Inputs* inputs; 154}; 155 156static const Inputs kCondition[] = {{NFlag, 0xabababab, 0xabababab}, 157 {ZFlag, 0xabababab, 0xabababab}, 158 {CFlag, 0xabababab, 0xabababab}, 159 {VFlag, 0xabababab, 0xabababab}, 160 {NZFlag, 0xabababab, 0xabababab}, 161 {NCFlag, 0xabababab, 0xabababab}, 162 {NVFlag, 0xabababab, 0xabababab}, 163 {ZCFlag, 0xabababab, 0xabababab}, 164 {ZVFlag, 0xabababab, 0xabababab}, 165 {CVFlag, 0xabababab, 0xabababab}, 166 {NZCFlag, 0xabababab, 0xabababab}, 167 {NZVFlag, 0xabababab, 0xabababab}, 168 {NCVFlag, 0xabababab, 0xabababab}, 169 {ZCVFlag, 0xabababab, 0xabababab}, 170 {NZCVFlag, 0xabababab, 0xabababab}}; 171 172static const Inputs kRdIsRn[] = {{NoFlag, 0x00000000, 0x00000000}, 173 {NoFlag, 0x00000001, 0x00000001}, 174 {NoFlag, 0x00000002, 0x00000002}, 175 {NoFlag, 0x00000020, 0x00000020}, 176 {NoFlag, 0x0000007d, 0x0000007d}, 177 {NoFlag, 0x0000007e, 0x0000007e}, 178 {NoFlag, 0x0000007f, 0x0000007f}, 179 {NoFlag, 0x00007ffd, 0x00007ffd}, 180 {NoFlag, 0x00007ffe, 0x00007ffe}, 181 {NoFlag, 0x00007fff, 0x00007fff}, 182 {NoFlag, 0x33333333, 0x33333333}, 183 {NoFlag, 0x55555555, 0x55555555}, 184 {NoFlag, 0x7ffffffd, 0x7ffffffd}, 185 {NoFlag, 0x7ffffffe, 0x7ffffffe}, 186 {NoFlag, 0x7fffffff, 0x7fffffff}, 187 {NoFlag, 0x80000000, 0x80000000}, 188 {NoFlag, 0x80000001, 0x80000001}, 189 {NoFlag, 0xaaaaaaaa, 0xaaaaaaaa}, 190 {NoFlag, 0xcccccccc, 0xcccccccc}, 191 {NoFlag, 0xffff8000, 0xffff8000}, 192 {NoFlag, 0xffff8001, 0xffff8001}, 193 {NoFlag, 0xffff8002, 0xffff8002}, 194 {NoFlag, 0xffff8003, 0xffff8003}, 195 {NoFlag, 0xffffff80, 0xffffff80}, 196 {NoFlag, 0xffffff81, 0xffffff81}, 197 {NoFlag, 0xffffff82, 0xffffff82}, 198 {NoFlag, 0xffffff83, 0xffffff83}, 199 {NoFlag, 0xffffffe0, 0xffffffe0}, 200 {NoFlag, 0xfffffffd, 0xfffffffd}, 201 {NoFlag, 0xfffffffe, 0xfffffffe}, 202 {NoFlag, 0xffffffff, 0xffffffff}}; 203 204static const Inputs kRdIsNotRn[] = {{NoFlag, 0x00000002, 0xcccccccc}, 205 {NoFlag, 0x7ffffffd, 0x00007ffe}, 206 {NoFlag, 0xffffff80, 0x00000020}, 207 {NoFlag, 0xaaaaaaaa, 0xaaaaaaaa}, 208 {NoFlag, 0x33333333, 0xffffff82}, 209 {NoFlag, 0xffff8001, 0x7ffffffe}, 210 {NoFlag, 0xfffffffd, 0x00007ffe}, 211 {NoFlag, 0xffffff80, 0x80000000}, 212 {NoFlag, 0x00000001, 0x33333333}, 213 {NoFlag, 0xcccccccc, 0x7ffffffe}, 214 {NoFlag, 0x00000000, 0xcccccccc}, 215 {NoFlag, 0x00000000, 0x55555555}, 216 {NoFlag, 0xffffffff, 0xffffffff}, 217 {NoFlag, 0x0000007e, 0xffff8002}, 218 {NoFlag, 0x80000000, 0x7ffffffd}, 219 {NoFlag, 0xffffff81, 0x0000007e}, 220 {NoFlag, 0x0000007f, 0xffff8001}, 221 {NoFlag, 0xffffffe0, 0x00007ffd}, 222 {NoFlag, 0xffff8003, 0x00000002}, 223 {NoFlag, 0xffffff83, 0x55555555}, 224 {NoFlag, 0xffffff83, 0xffffff80}, 225 {NoFlag, 0xffffff81, 0xffff8000}, 226 {NoFlag, 0x00000020, 0x7ffffffe}, 227 {NoFlag, 0xffffffe0, 0x00000000}, 228 {NoFlag, 0x7fffffff, 0x0000007e}, 229 {NoFlag, 0x80000001, 0xffffffff}, 230 {NoFlag, 0x00000001, 0x80000001}, 231 {NoFlag, 0x00000002, 0x0000007f}, 232 {NoFlag, 0x7fffffff, 0xcccccccc}, 233 {NoFlag, 0x80000001, 0x00007ffe}, 234 {NoFlag, 0xffff8002, 0x0000007e}, 235 {NoFlag, 0x00007ffe, 0xcccccccc}, 236 {NoFlag, 0x80000000, 0xffff8002}, 237 {NoFlag, 0xffffff83, 0x7ffffffe}, 238 {NoFlag, 0xffff8001, 0x00000001}, 239 {NoFlag, 0xffffff81, 0x00000020}, 240 {NoFlag, 0xfffffffe, 0xffff8001}, 241 {NoFlag, 0xffffffff, 0xfffffffe}, 242 {NoFlag, 0xcccccccc, 0x55555555}, 243 {NoFlag, 0x00000020, 0xffffff83}, 244 {NoFlag, 0xffffff83, 0xffff8001}, 245 {NoFlag, 0xffffff83, 0xffff8000}, 246 {NoFlag, 0x00007fff, 0x00000002}, 247 {NoFlag, 0x55555555, 0xffff8000}, 248 {NoFlag, 0x80000001, 0xffffff81}, 249 {NoFlag, 0x00000002, 0x00000000}, 250 {NoFlag, 0x33333333, 0xffffff81}, 251 {NoFlag, 0xffff8001, 0xffffff82}, 252 {NoFlag, 0xcccccccc, 0xffff8003}, 253 {NoFlag, 0xffff8003, 0x7ffffffd}, 254 {NoFlag, 0x0000007d, 0x00007ffe}, 255 {NoFlag, 0xffffff80, 0x0000007d}, 256 {NoFlag, 0xaaaaaaaa, 0x00007ffd}, 257 {NoFlag, 0x80000000, 0xffffff82}, 258 {NoFlag, 0x00000002, 0x7ffffffe}, 259 {NoFlag, 0x00000002, 0xffffff83}, 260 {NoFlag, 0x55555555, 0x00000002}, 261 {NoFlag, 0xffffffff, 0xffffff82}, 262 {NoFlag, 0xaaaaaaaa, 0x00000020}, 263 {NoFlag, 0x00000001, 0xffffff82}, 264 {NoFlag, 0x0000007f, 0xffffff82}, 265 {NoFlag, 0x7ffffffd, 0xaaaaaaaa}, 266 {NoFlag, 0x00007ffe, 0x00000001}, 267 {NoFlag, 0xfffffffd, 0xffffffe0}, 268 {NoFlag, 0xffffff81, 0xffffff83}, 269 {NoFlag, 0x0000007d, 0x00000000}, 270 {NoFlag, 0x0000007d, 0xffff8000}, 271 {NoFlag, 0xffffff81, 0x7fffffff}, 272 {NoFlag, 0xffffffff, 0x80000000}, 273 {NoFlag, 0x00000000, 0x00000001}, 274 {NoFlag, 0x55555555, 0xffffff82}, 275 {NoFlag, 0x00007ffe, 0x00007ffe}, 276 {NoFlag, 0x80000001, 0xfffffffd}, 277 {NoFlag, 0x00007fff, 0x33333333}, 278 {NoFlag, 0x00007fff, 0x80000000}, 279 {NoFlag, 0xcccccccc, 0x00007fff}, 280 {NoFlag, 0xfffffffe, 0xffffffe0}, 281 {NoFlag, 0x7ffffffe, 0x0000007f}, 282 {NoFlag, 0x00007ffd, 0xffff8001}, 283 {NoFlag, 0x00000002, 0x00000001}, 284 {NoFlag, 0x80000000, 0xffffffff}, 285 {NoFlag, 0xffffff83, 0xcccccccc}, 286 {NoFlag, 0xffff8002, 0x7ffffffe}, 287 {NoFlag, 0xaaaaaaaa, 0x00000000}, 288 {NoFlag, 0xffffff80, 0xcccccccc}, 289 {NoFlag, 0x33333333, 0xffffff83}, 290 {NoFlag, 0x0000007e, 0xffffffe0}, 291 {NoFlag, 0x0000007e, 0x00007fff}, 292 {NoFlag, 0x0000007f, 0x00000002}, 293 {NoFlag, 0x7ffffffe, 0xcccccccc}, 294 {NoFlag, 0x0000007d, 0xffffff80}, 295 {NoFlag, 0x00007fff, 0x00000020}, 296 {NoFlag, 0x7ffffffe, 0xfffffffe}, 297 {NoFlag, 0xfffffffe, 0xffffff81}, 298 {NoFlag, 0xffffffff, 0x0000007f}, 299 {NoFlag, 0xffff8002, 0x7ffffffd}, 300 {NoFlag, 0xffff8001, 0xfffffffe}, 301 {NoFlag, 0x33333333, 0xffff8002}, 302 {NoFlag, 0x00000000, 0xffffffff}, 303 {NoFlag, 0x33333333, 0xffffff80}, 304 {NoFlag, 0x0000007f, 0x00007fff}, 305 {NoFlag, 0xffffffff, 0xffff8001}, 306 {NoFlag, 0x7fffffff, 0xffff8002}, 307 {NoFlag, 0x7ffffffd, 0xffffff83}, 308 {NoFlag, 0x7fffffff, 0x0000007f}, 309 {NoFlag, 0xffffff83, 0xfffffffe}, 310 {NoFlag, 0x7ffffffe, 0xffff8003}, 311 {NoFlag, 0xffff8002, 0xffff8002}, 312 {NoFlag, 0x80000001, 0x0000007f}, 313 {NoFlag, 0x00000020, 0x00000002}, 314 {NoFlag, 0xffffff82, 0xffff8001}, 315 {NoFlag, 0xffffffff, 0x00000001}, 316 {NoFlag, 0xffffff80, 0xffff8002}, 317 {NoFlag, 0xffff8003, 0x7fffffff}, 318 {NoFlag, 0xffffffff, 0xffff8000}, 319 {NoFlag, 0xffff8002, 0x00007ffd}, 320 {NoFlag, 0x00000020, 0xffffff81}, 321 {NoFlag, 0x00000001, 0x55555555}, 322 {NoFlag, 0x7ffffffe, 0x00000020}, 323 {NoFlag, 0x80000000, 0x00000001}, 324 {NoFlag, 0x00007ffd, 0xffff8002}, 325 {NoFlag, 0x7fffffff, 0xfffffffe}, 326 {NoFlag, 0xcccccccc, 0x00007ffd}, 327 {NoFlag, 0x00000000, 0xfffffffd}, 328 {NoFlag, 0xffff8003, 0xffffff80}, 329 {NoFlag, 0x80000001, 0xffffff80}, 330 {NoFlag, 0xffffffff, 0xffff8002}, 331 {NoFlag, 0x00007ffe, 0xffff8002}, 332 {NoFlag, 0xffffff80, 0x00007ffe}, 333 {NoFlag, 0x80000001, 0xffff8001}, 334 {NoFlag, 0x0000007f, 0xffffff80}, 335 {NoFlag, 0xffffff81, 0x80000000}, 336 {NoFlag, 0x00007fff, 0x00007ffe}, 337 {NoFlag, 0x33333333, 0xffff8000}, 338 {NoFlag, 0x33333333, 0x00007fff}, 339 {NoFlag, 0x00000000, 0x0000007d}, 340 {NoFlag, 0x80000001, 0x00000000}, 341 {NoFlag, 0xffffffff, 0x55555555}, 342 {NoFlag, 0x80000001, 0x80000000}, 343 {NoFlag, 0xffffffff, 0xffffff80}, 344 {NoFlag, 0xffffff81, 0xffff8003}, 345 {NoFlag, 0x55555555, 0x80000001}, 346 {NoFlag, 0x7fffffff, 0xffff8001}, 347 {NoFlag, 0xffffff83, 0x00000002}, 348 {NoFlag, 0x0000007e, 0xffffff81}, 349 {NoFlag, 0x80000000, 0xffff8001}, 350 {NoFlag, 0xffffff80, 0xfffffffe}, 351 {NoFlag, 0x0000007e, 0xfffffffd}, 352 {NoFlag, 0xffffffe0, 0xffffffff}, 353 {NoFlag, 0x55555555, 0x80000000}, 354 {NoFlag, 0x0000007d, 0x80000001}, 355 {NoFlag, 0xffffffe0, 0x7ffffffd}, 356 {NoFlag, 0x00000000, 0x00000000}, 357 {NoFlag, 0x55555555, 0x00000001}, 358 {NoFlag, 0x00007ffd, 0x7fffffff}, 359 {NoFlag, 0x55555555, 0xffffffff}, 360 {NoFlag, 0xffff8003, 0x00007fff}, 361 {NoFlag, 0xffffff82, 0x00007fff}, 362 {NoFlag, 0x33333333, 0x55555555}, 363 {NoFlag, 0x00000020, 0x33333333}, 364 {NoFlag, 0x7ffffffe, 0xfffffffd}, 365 {NoFlag, 0x7ffffffe, 0x00000001}, 366 {NoFlag, 0xffffff83, 0xffffffe0}, 367 {NoFlag, 0xfffffffe, 0xaaaaaaaa}, 368 {NoFlag, 0xffff8002, 0x33333333}, 369 {NoFlag, 0xffff8002, 0xffff8003}, 370 {NoFlag, 0x33333333, 0x7fffffff}, 371 {NoFlag, 0xfffffffd, 0xffffff83}, 372 {NoFlag, 0x00000000, 0xffff8000}, 373 {NoFlag, 0xffffff82, 0x55555555}, 374 {NoFlag, 0xffffff82, 0xffffff81}, 375 {NoFlag, 0xcccccccc, 0xfffffffe}, 376 {NoFlag, 0xfffffffd, 0x7fffffff}, 377 {NoFlag, 0x00007fff, 0x7fffffff}, 378 {NoFlag, 0xffffff83, 0xffff8003}, 379 {NoFlag, 0xfffffffe, 0xffffffff}, 380 {NoFlag, 0x7ffffffd, 0x00007ffd}, 381 {NoFlag, 0x7ffffffd, 0x00007fff}, 382 {NoFlag, 0x00007ffd, 0xffffffff}, 383 {NoFlag, 0x00000001, 0xffff8003}, 384 {NoFlag, 0xffffff80, 0xfffffffd}, 385 {NoFlag, 0x33333333, 0x80000000}, 386 {NoFlag, 0xffff8001, 0x00000020}, 387 {NoFlag, 0xcccccccc, 0x00000002}, 388 {NoFlag, 0x00000000, 0x00000002}, 389 {NoFlag, 0x0000007d, 0x00007fff}, 390 {NoFlag, 0xcccccccc, 0x00000001}, 391 {NoFlag, 0xffffff83, 0x00007fff}, 392 {NoFlag, 0x80000001, 0x00000020}, 393 {NoFlag, 0xffff8003, 0xffffffe0}, 394 {NoFlag, 0x00007ffd, 0xaaaaaaaa}, 395 {NoFlag, 0x33333333, 0xffff8001}, 396 {NoFlag, 0xffffff83, 0x80000001}, 397 {NoFlag, 0xffff8000, 0xffff8000}, 398 {NoFlag, 0x00007ffe, 0xffff8001}, 399 {NoFlag, 0x7ffffffd, 0x00000000}, 400 {NoFlag, 0x00007ffe, 0x33333333}, 401 {NoFlag, 0xffff8001, 0xffffff80}, 402 {NoFlag, 0xfffffffe, 0x55555555}, 403 {NoFlag, 0xffffff82, 0xffffffff}}; 404 405static const Inputs kShiftTypes[] = {{NoFlag, 0xabababab, 0x00000000}, 406 {NoFlag, 0xabababab, 0x00000001}, 407 {NoFlag, 0xabababab, 0x00000002}, 408 {NoFlag, 0xabababab, 0x00000020}, 409 {NoFlag, 0xabababab, 0x0000007d}, 410 {NoFlag, 0xabababab, 0x0000007e}, 411 {NoFlag, 0xabababab, 0x0000007f}, 412 {NoFlag, 0xabababab, 0x00007ffd}, 413 {NoFlag, 0xabababab, 0x00007ffe}, 414 {NoFlag, 0xabababab, 0x00007fff}, 415 {NoFlag, 0xabababab, 0x33333333}, 416 {NoFlag, 0xabababab, 0x55555555}, 417 {NoFlag, 0xabababab, 0x7ffffffd}, 418 {NoFlag, 0xabababab, 0x7ffffffe}, 419 {NoFlag, 0xabababab, 0x7fffffff}, 420 {NoFlag, 0xabababab, 0x80000000}, 421 {NoFlag, 0xabababab, 0x80000001}, 422 {NoFlag, 0xabababab, 0xaaaaaaaa}, 423 {NoFlag, 0xabababab, 0xcccccccc}, 424 {NoFlag, 0xabababab, 0xffff8000}, 425 {NoFlag, 0xabababab, 0xffff8001}, 426 {NoFlag, 0xabababab, 0xffff8002}, 427 {NoFlag, 0xabababab, 0xffff8003}, 428 {NoFlag, 0xabababab, 0xffffff80}, 429 {NoFlag, 0xabababab, 0xffffff81}, 430 {NoFlag, 0xabababab, 0xffffff82}, 431 {NoFlag, 0xabababab, 0xffffff83}, 432 {NoFlag, 0xabababab, 0xffffffe0}, 433 {NoFlag, 0xabababab, 0xfffffffd}, 434 {NoFlag, 0xabababab, 0xfffffffe}, 435 {NoFlag, 0xabababab, 0xffffffff}}; 436 437 438// A loop will be generated for each element of this array. 439static const TestLoopData kTests[] = {{{eq, r0, r0, LSL, 1}, 440 "eq r0 r0 LSL 1", 441 "Condition_eq_r0_r0_LSL_1", 442 ARRAY_SIZE(kCondition), 443 kCondition}, 444 {{ne, r0, r0, LSL, 1}, 445 "ne r0 r0 LSL 1", 446 "Condition_ne_r0_r0_LSL_1", 447 ARRAY_SIZE(kCondition), 448 kCondition}, 449 {{cs, r0, r0, LSL, 1}, 450 "cs r0 r0 LSL 1", 451 "Condition_cs_r0_r0_LSL_1", 452 ARRAY_SIZE(kCondition), 453 kCondition}, 454 {{cc, r0, r0, LSL, 1}, 455 "cc r0 r0 LSL 1", 456 "Condition_cc_r0_r0_LSL_1", 457 ARRAY_SIZE(kCondition), 458 kCondition}, 459 {{mi, r0, r0, LSL, 1}, 460 "mi r0 r0 LSL 1", 461 "Condition_mi_r0_r0_LSL_1", 462 ARRAY_SIZE(kCondition), 463 kCondition}, 464 {{pl, r0, r0, LSL, 1}, 465 "pl r0 r0 LSL 1", 466 "Condition_pl_r0_r0_LSL_1", 467 ARRAY_SIZE(kCondition), 468 kCondition}, 469 {{vs, r0, r0, LSL, 1}, 470 "vs r0 r0 LSL 1", 471 "Condition_vs_r0_r0_LSL_1", 472 ARRAY_SIZE(kCondition), 473 kCondition}, 474 {{vc, r0, r0, LSL, 1}, 475 "vc r0 r0 LSL 1", 476 "Condition_vc_r0_r0_LSL_1", 477 ARRAY_SIZE(kCondition), 478 kCondition}, 479 {{hi, r0, r0, LSL, 1}, 480 "hi r0 r0 LSL 1", 481 "Condition_hi_r0_r0_LSL_1", 482 ARRAY_SIZE(kCondition), 483 kCondition}, 484 {{ls, r0, r0, LSL, 1}, 485 "ls r0 r0 LSL 1", 486 "Condition_ls_r0_r0_LSL_1", 487 ARRAY_SIZE(kCondition), 488 kCondition}, 489 {{ge, r0, r0, LSL, 1}, 490 "ge r0 r0 LSL 1", 491 "Condition_ge_r0_r0_LSL_1", 492 ARRAY_SIZE(kCondition), 493 kCondition}, 494 {{lt, r0, r0, LSL, 1}, 495 "lt r0 r0 LSL 1", 496 "Condition_lt_r0_r0_LSL_1", 497 ARRAY_SIZE(kCondition), 498 kCondition}, 499 {{gt, r0, r0, LSL, 1}, 500 "gt r0 r0 LSL 1", 501 "Condition_gt_r0_r0_LSL_1", 502 ARRAY_SIZE(kCondition), 503 kCondition}, 504 {{le, r0, r0, LSL, 1}, 505 "le r0 r0 LSL 1", 506 "Condition_le_r0_r0_LSL_1", 507 ARRAY_SIZE(kCondition), 508 kCondition}, 509 {{al, r0, r0, LSL, 1}, 510 "al r0 r0 LSL 1", 511 "Condition_al_r0_r0_LSL_1", 512 ARRAY_SIZE(kCondition), 513 kCondition}, 514 {{al, r0, r0, LSL, 1}, 515 "al r0 r0 LSL 1", 516 "RdIsRn_al_r0_r0_LSL_1", 517 ARRAY_SIZE(kRdIsRn), 518 kRdIsRn}, 519 {{al, r1, r1, LSL, 1}, 520 "al r1 r1 LSL 1", 521 "RdIsRn_al_r1_r1_LSL_1", 522 ARRAY_SIZE(kRdIsRn), 523 kRdIsRn}, 524 {{al, r2, r2, LSL, 1}, 525 "al r2 r2 LSL 1", 526 "RdIsRn_al_r2_r2_LSL_1", 527 ARRAY_SIZE(kRdIsRn), 528 kRdIsRn}, 529 {{al, r3, r3, LSL, 1}, 530 "al r3 r3 LSL 1", 531 "RdIsRn_al_r3_r3_LSL_1", 532 ARRAY_SIZE(kRdIsRn), 533 kRdIsRn}, 534 {{al, r4, r4, LSL, 1}, 535 "al r4 r4 LSL 1", 536 "RdIsRn_al_r4_r4_LSL_1", 537 ARRAY_SIZE(kRdIsRn), 538 kRdIsRn}, 539 {{al, r5, r5, LSL, 1}, 540 "al r5 r5 LSL 1", 541 "RdIsRn_al_r5_r5_LSL_1", 542 ARRAY_SIZE(kRdIsRn), 543 kRdIsRn}, 544 {{al, r6, r6, LSL, 1}, 545 "al r6 r6 LSL 1", 546 "RdIsRn_al_r6_r6_LSL_1", 547 ARRAY_SIZE(kRdIsRn), 548 kRdIsRn}, 549 {{al, r7, r7, LSL, 1}, 550 "al r7 r7 LSL 1", 551 "RdIsRn_al_r7_r7_LSL_1", 552 ARRAY_SIZE(kRdIsRn), 553 kRdIsRn}, 554 {{al, r8, r8, LSL, 1}, 555 "al r8 r8 LSL 1", 556 "RdIsRn_al_r8_r8_LSL_1", 557 ARRAY_SIZE(kRdIsRn), 558 kRdIsRn}, 559 {{al, r9, r9, LSL, 1}, 560 "al r9 r9 LSL 1", 561 "RdIsRn_al_r9_r9_LSL_1", 562 ARRAY_SIZE(kRdIsRn), 563 kRdIsRn}, 564 {{al, r10, r10, LSL, 1}, 565 "al r10 r10 LSL 1", 566 "RdIsRn_al_r10_r10_LSL_1", 567 ARRAY_SIZE(kRdIsRn), 568 kRdIsRn}, 569 {{al, r11, r11, LSL, 1}, 570 "al r11 r11 LSL 1", 571 "RdIsRn_al_r11_r11_LSL_1", 572 ARRAY_SIZE(kRdIsRn), 573 kRdIsRn}, 574 {{al, r12, r12, LSL, 1}, 575 "al r12 r12 LSL 1", 576 "RdIsRn_al_r12_r12_LSL_1", 577 ARRAY_SIZE(kRdIsRn), 578 kRdIsRn}, 579 {{al, r14, r14, LSL, 1}, 580 "al r14 r14 LSL 1", 581 "RdIsRn_al_r14_r14_LSL_1", 582 ARRAY_SIZE(kRdIsRn), 583 kRdIsRn}, 584 {{al, r1, r8, LSL, 1}, 585 "al r1 r8 LSL 1", 586 "RdIsNotRn_al_r1_r8_LSL_1", 587 ARRAY_SIZE(kRdIsNotRn), 588 kRdIsNotRn}, 589 {{al, r7, r4, LSL, 1}, 590 "al r7 r4 LSL 1", 591 "RdIsNotRn_al_r7_r4_LSL_1", 592 ARRAY_SIZE(kRdIsNotRn), 593 kRdIsNotRn}, 594 {{al, r14, r10, LSL, 1}, 595 "al r14 r10 LSL 1", 596 "RdIsNotRn_al_r14_r10_LSL_1", 597 ARRAY_SIZE(kRdIsNotRn), 598 kRdIsNotRn}, 599 {{al, r10, r6, LSL, 1}, 600 "al r10 r6 LSL 1", 601 "RdIsNotRn_al_r10_r6_LSL_1", 602 ARRAY_SIZE(kRdIsNotRn), 603 kRdIsNotRn}, 604 {{al, r6, r5, LSL, 1}, 605 "al r6 r5 LSL 1", 606 "RdIsNotRn_al_r6_r5_LSL_1", 607 ARRAY_SIZE(kRdIsNotRn), 608 kRdIsNotRn}, 609 {{al, r12, r2, LSL, 1}, 610 "al r12 r2 LSL 1", 611 "RdIsNotRn_al_r12_r2_LSL_1", 612 ARRAY_SIZE(kRdIsNotRn), 613 kRdIsNotRn}, 614 {{al, r0, r11, LSL, 1}, 615 "al r0 r11 LSL 1", 616 "RdIsNotRn_al_r0_r11_LSL_1", 617 ARRAY_SIZE(kRdIsNotRn), 618 kRdIsNotRn}, 619 {{al, r10, r14, LSL, 1}, 620 "al r10 r14 LSL 1", 621 "RdIsNotRn_al_r10_r14_LSL_1", 622 ARRAY_SIZE(kRdIsNotRn), 623 kRdIsNotRn}, 624 {{al, r0, r5, LSL, 1}, 625 "al r0 r5 LSL 1", 626 "RdIsNotRn_al_r0_r5_LSL_1", 627 ARRAY_SIZE(kRdIsNotRn), 628 kRdIsNotRn}, 629 {{al, r0, r3, LSL, 1}, 630 "al r0 r3 LSL 1", 631 "RdIsNotRn_al_r0_r3_LSL_1", 632 ARRAY_SIZE(kRdIsNotRn), 633 kRdIsNotRn}, 634 {{al, r0, r0, LSL, 1}, 635 "al r0 r0 LSL 1", 636 "ShiftTypes_al_r0_r0_LSL_1", 637 ARRAY_SIZE(kShiftTypes), 638 kShiftTypes}, 639 {{al, r0, r0, LSL, 2}, 640 "al r0 r0 LSL 2", 641 "ShiftTypes_al_r0_r0_LSL_2", 642 ARRAY_SIZE(kShiftTypes), 643 kShiftTypes}, 644 {{al, r0, r0, LSL, 3}, 645 "al r0 r0 LSL 3", 646 "ShiftTypes_al_r0_r0_LSL_3", 647 ARRAY_SIZE(kShiftTypes), 648 kShiftTypes}, 649 {{al, r0, r0, LSL, 4}, 650 "al r0 r0 LSL 4", 651 "ShiftTypes_al_r0_r0_LSL_4", 652 ARRAY_SIZE(kShiftTypes), 653 kShiftTypes}, 654 {{al, r0, r0, LSL, 5}, 655 "al r0 r0 LSL 5", 656 "ShiftTypes_al_r0_r0_LSL_5", 657 ARRAY_SIZE(kShiftTypes), 658 kShiftTypes}, 659 {{al, r0, r0, LSL, 6}, 660 "al r0 r0 LSL 6", 661 "ShiftTypes_al_r0_r0_LSL_6", 662 ARRAY_SIZE(kShiftTypes), 663 kShiftTypes}, 664 {{al, r0, r0, LSL, 7}, 665 "al r0 r0 LSL 7", 666 "ShiftTypes_al_r0_r0_LSL_7", 667 ARRAY_SIZE(kShiftTypes), 668 kShiftTypes}, 669 {{al, r0, r0, LSL, 8}, 670 "al r0 r0 LSL 8", 671 "ShiftTypes_al_r0_r0_LSL_8", 672 ARRAY_SIZE(kShiftTypes), 673 kShiftTypes}, 674 {{al, r0, r0, LSL, 9}, 675 "al r0 r0 LSL 9", 676 "ShiftTypes_al_r0_r0_LSL_9", 677 ARRAY_SIZE(kShiftTypes), 678 kShiftTypes}, 679 {{al, r0, r0, LSL, 10}, 680 "al r0 r0 LSL 10", 681 "ShiftTypes_al_r0_r0_LSL_10", 682 ARRAY_SIZE(kShiftTypes), 683 kShiftTypes}, 684 {{al, r0, r0, LSL, 11}, 685 "al r0 r0 LSL 11", 686 "ShiftTypes_al_r0_r0_LSL_11", 687 ARRAY_SIZE(kShiftTypes), 688 kShiftTypes}, 689 {{al, r0, r0, LSL, 12}, 690 "al r0 r0 LSL 12", 691 "ShiftTypes_al_r0_r0_LSL_12", 692 ARRAY_SIZE(kShiftTypes), 693 kShiftTypes}, 694 {{al, r0, r0, LSL, 13}, 695 "al r0 r0 LSL 13", 696 "ShiftTypes_al_r0_r0_LSL_13", 697 ARRAY_SIZE(kShiftTypes), 698 kShiftTypes}, 699 {{al, r0, r0, LSL, 14}, 700 "al r0 r0 LSL 14", 701 "ShiftTypes_al_r0_r0_LSL_14", 702 ARRAY_SIZE(kShiftTypes), 703 kShiftTypes}, 704 {{al, r0, r0, LSL, 15}, 705 "al r0 r0 LSL 15", 706 "ShiftTypes_al_r0_r0_LSL_15", 707 ARRAY_SIZE(kShiftTypes), 708 kShiftTypes}, 709 {{al, r0, r0, LSL, 16}, 710 "al r0 r0 LSL 16", 711 "ShiftTypes_al_r0_r0_LSL_16", 712 ARRAY_SIZE(kShiftTypes), 713 kShiftTypes}, 714 {{al, r0, r0, LSL, 17}, 715 "al r0 r0 LSL 17", 716 "ShiftTypes_al_r0_r0_LSL_17", 717 ARRAY_SIZE(kShiftTypes), 718 kShiftTypes}, 719 {{al, r0, r0, LSL, 18}, 720 "al r0 r0 LSL 18", 721 "ShiftTypes_al_r0_r0_LSL_18", 722 ARRAY_SIZE(kShiftTypes), 723 kShiftTypes}, 724 {{al, r0, r0, LSL, 19}, 725 "al r0 r0 LSL 19", 726 "ShiftTypes_al_r0_r0_LSL_19", 727 ARRAY_SIZE(kShiftTypes), 728 kShiftTypes}, 729 {{al, r0, r0, LSL, 20}, 730 "al r0 r0 LSL 20", 731 "ShiftTypes_al_r0_r0_LSL_20", 732 ARRAY_SIZE(kShiftTypes), 733 kShiftTypes}, 734 {{al, r0, r0, LSL, 21}, 735 "al r0 r0 LSL 21", 736 "ShiftTypes_al_r0_r0_LSL_21", 737 ARRAY_SIZE(kShiftTypes), 738 kShiftTypes}, 739 {{al, r0, r0, LSL, 22}, 740 "al r0 r0 LSL 22", 741 "ShiftTypes_al_r0_r0_LSL_22", 742 ARRAY_SIZE(kShiftTypes), 743 kShiftTypes}, 744 {{al, r0, r0, LSL, 23}, 745 "al r0 r0 LSL 23", 746 "ShiftTypes_al_r0_r0_LSL_23", 747 ARRAY_SIZE(kShiftTypes), 748 kShiftTypes}, 749 {{al, r0, r0, LSL, 24}, 750 "al r0 r0 LSL 24", 751 "ShiftTypes_al_r0_r0_LSL_24", 752 ARRAY_SIZE(kShiftTypes), 753 kShiftTypes}, 754 {{al, r0, r0, LSL, 25}, 755 "al r0 r0 LSL 25", 756 "ShiftTypes_al_r0_r0_LSL_25", 757 ARRAY_SIZE(kShiftTypes), 758 kShiftTypes}, 759 {{al, r0, r0, LSL, 26}, 760 "al r0 r0 LSL 26", 761 "ShiftTypes_al_r0_r0_LSL_26", 762 ARRAY_SIZE(kShiftTypes), 763 kShiftTypes}, 764 {{al, r0, r0, LSL, 27}, 765 "al r0 r0 LSL 27", 766 "ShiftTypes_al_r0_r0_LSL_27", 767 ARRAY_SIZE(kShiftTypes), 768 kShiftTypes}, 769 {{al, r0, r0, LSL, 28}, 770 "al r0 r0 LSL 28", 771 "ShiftTypes_al_r0_r0_LSL_28", 772 ARRAY_SIZE(kShiftTypes), 773 kShiftTypes}, 774 {{al, r0, r0, LSL, 29}, 775 "al r0 r0 LSL 29", 776 "ShiftTypes_al_r0_r0_LSL_29", 777 ARRAY_SIZE(kShiftTypes), 778 kShiftTypes}, 779 {{al, r0, r0, LSL, 30}, 780 "al r0 r0 LSL 30", 781 "ShiftTypes_al_r0_r0_LSL_30", 782 ARRAY_SIZE(kShiftTypes), 783 kShiftTypes}, 784 {{al, r0, r0, LSL, 31}, 785 "al r0 r0 LSL 31", 786 "ShiftTypes_al_r0_r0_LSL_31", 787 ARRAY_SIZE(kShiftTypes), 788 kShiftTypes}, 789 {{al, r0, r0, ROR, 1}, 790 "al r0 r0 ROR 1", 791 "ShiftTypes_al_r0_r0_ROR_1", 792 ARRAY_SIZE(kShiftTypes), 793 kShiftTypes}, 794 {{al, r0, r0, ROR, 2}, 795 "al r0 r0 ROR 2", 796 "ShiftTypes_al_r0_r0_ROR_2", 797 ARRAY_SIZE(kShiftTypes), 798 kShiftTypes}, 799 {{al, r0, r0, ROR, 3}, 800 "al r0 r0 ROR 3", 801 "ShiftTypes_al_r0_r0_ROR_3", 802 ARRAY_SIZE(kShiftTypes), 803 kShiftTypes}, 804 {{al, r0, r0, ROR, 4}, 805 "al r0 r0 ROR 4", 806 "ShiftTypes_al_r0_r0_ROR_4", 807 ARRAY_SIZE(kShiftTypes), 808 kShiftTypes}, 809 {{al, r0, r0, ROR, 5}, 810 "al r0 r0 ROR 5", 811 "ShiftTypes_al_r0_r0_ROR_5", 812 ARRAY_SIZE(kShiftTypes), 813 kShiftTypes}, 814 {{al, r0, r0, ROR, 6}, 815 "al r0 r0 ROR 6", 816 "ShiftTypes_al_r0_r0_ROR_6", 817 ARRAY_SIZE(kShiftTypes), 818 kShiftTypes}, 819 {{al, r0, r0, ROR, 7}, 820 "al r0 r0 ROR 7", 821 "ShiftTypes_al_r0_r0_ROR_7", 822 ARRAY_SIZE(kShiftTypes), 823 kShiftTypes}, 824 {{al, r0, r0, ROR, 8}, 825 "al r0 r0 ROR 8", 826 "ShiftTypes_al_r0_r0_ROR_8", 827 ARRAY_SIZE(kShiftTypes), 828 kShiftTypes}, 829 {{al, r0, r0, ROR, 9}, 830 "al r0 r0 ROR 9", 831 "ShiftTypes_al_r0_r0_ROR_9", 832 ARRAY_SIZE(kShiftTypes), 833 kShiftTypes}, 834 {{al, r0, r0, ROR, 10}, 835 "al r0 r0 ROR 10", 836 "ShiftTypes_al_r0_r0_ROR_10", 837 ARRAY_SIZE(kShiftTypes), 838 kShiftTypes}, 839 {{al, r0, r0, ROR, 11}, 840 "al r0 r0 ROR 11", 841 "ShiftTypes_al_r0_r0_ROR_11", 842 ARRAY_SIZE(kShiftTypes), 843 kShiftTypes}, 844 {{al, r0, r0, ROR, 12}, 845 "al r0 r0 ROR 12", 846 "ShiftTypes_al_r0_r0_ROR_12", 847 ARRAY_SIZE(kShiftTypes), 848 kShiftTypes}, 849 {{al, r0, r0, ROR, 13}, 850 "al r0 r0 ROR 13", 851 "ShiftTypes_al_r0_r0_ROR_13", 852 ARRAY_SIZE(kShiftTypes), 853 kShiftTypes}, 854 {{al, r0, r0, ROR, 14}, 855 "al r0 r0 ROR 14", 856 "ShiftTypes_al_r0_r0_ROR_14", 857 ARRAY_SIZE(kShiftTypes), 858 kShiftTypes}, 859 {{al, r0, r0, ROR, 15}, 860 "al r0 r0 ROR 15", 861 "ShiftTypes_al_r0_r0_ROR_15", 862 ARRAY_SIZE(kShiftTypes), 863 kShiftTypes}, 864 {{al, r0, r0, ROR, 16}, 865 "al r0 r0 ROR 16", 866 "ShiftTypes_al_r0_r0_ROR_16", 867 ARRAY_SIZE(kShiftTypes), 868 kShiftTypes}, 869 {{al, r0, r0, ROR, 17}, 870 "al r0 r0 ROR 17", 871 "ShiftTypes_al_r0_r0_ROR_17", 872 ARRAY_SIZE(kShiftTypes), 873 kShiftTypes}, 874 {{al, r0, r0, ROR, 18}, 875 "al r0 r0 ROR 18", 876 "ShiftTypes_al_r0_r0_ROR_18", 877 ARRAY_SIZE(kShiftTypes), 878 kShiftTypes}, 879 {{al, r0, r0, ROR, 19}, 880 "al r0 r0 ROR 19", 881 "ShiftTypes_al_r0_r0_ROR_19", 882 ARRAY_SIZE(kShiftTypes), 883 kShiftTypes}, 884 {{al, r0, r0, ROR, 20}, 885 "al r0 r0 ROR 20", 886 "ShiftTypes_al_r0_r0_ROR_20", 887 ARRAY_SIZE(kShiftTypes), 888 kShiftTypes}, 889 {{al, r0, r0, ROR, 21}, 890 "al r0 r0 ROR 21", 891 "ShiftTypes_al_r0_r0_ROR_21", 892 ARRAY_SIZE(kShiftTypes), 893 kShiftTypes}, 894 {{al, r0, r0, ROR, 22}, 895 "al r0 r0 ROR 22", 896 "ShiftTypes_al_r0_r0_ROR_22", 897 ARRAY_SIZE(kShiftTypes), 898 kShiftTypes}, 899 {{al, r0, r0, ROR, 23}, 900 "al r0 r0 ROR 23", 901 "ShiftTypes_al_r0_r0_ROR_23", 902 ARRAY_SIZE(kShiftTypes), 903 kShiftTypes}, 904 {{al, r0, r0, ROR, 24}, 905 "al r0 r0 ROR 24", 906 "ShiftTypes_al_r0_r0_ROR_24", 907 ARRAY_SIZE(kShiftTypes), 908 kShiftTypes}, 909 {{al, r0, r0, ROR, 25}, 910 "al r0 r0 ROR 25", 911 "ShiftTypes_al_r0_r0_ROR_25", 912 ARRAY_SIZE(kShiftTypes), 913 kShiftTypes}, 914 {{al, r0, r0, ROR, 26}, 915 "al r0 r0 ROR 26", 916 "ShiftTypes_al_r0_r0_ROR_26", 917 ARRAY_SIZE(kShiftTypes), 918 kShiftTypes}, 919 {{al, r0, r0, ROR, 27}, 920 "al r0 r0 ROR 27", 921 "ShiftTypes_al_r0_r0_ROR_27", 922 ARRAY_SIZE(kShiftTypes), 923 kShiftTypes}, 924 {{al, r0, r0, ROR, 28}, 925 "al r0 r0 ROR 28", 926 "ShiftTypes_al_r0_r0_ROR_28", 927 ARRAY_SIZE(kShiftTypes), 928 kShiftTypes}, 929 {{al, r0, r0, ROR, 29}, 930 "al r0 r0 ROR 29", 931 "ShiftTypes_al_r0_r0_ROR_29", 932 ARRAY_SIZE(kShiftTypes), 933 kShiftTypes}, 934 {{al, r0, r0, ROR, 30}, 935 "al r0 r0 ROR 30", 936 "ShiftTypes_al_r0_r0_ROR_30", 937 ARRAY_SIZE(kShiftTypes), 938 kShiftTypes}, 939 {{al, r0, r0, ROR, 31}, 940 "al r0 r0 ROR 31", 941 "ShiftTypes_al_r0_r0_ROR_31", 942 ARRAY_SIZE(kShiftTypes), 943 kShiftTypes}}; 944 945// We record all inputs to the instructions as outputs. This way, we also check 946// that what shouldn't change didn't change. 947struct TestResult { 948 size_t output_size; 949 const Inputs* outputs; 950}; 951 952// These headers each contain an array of `TestResult` with the reference output 953// values. The reference arrays are names `kReference{mnemonic}`. 954#include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmn.h" 955#include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-cmp.h" 956#include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mov.h" 957#include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-movs.h" 958#include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvn.h" 959#include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h" 960#include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-teq.h" 961#include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-a32-tst.h" 962 963 964// The maximum number of errors to report in detail for each test. 965static const unsigned kErrorReportLimit = 8; 966 967typedef void (MacroAssembler::*Fn)(Condition cond, 968 Register rd, 969 const Operand& op); 970 971static void TestHelper(Fn instruction, 972 const char* mnemonic, 973 const TestResult reference[]) { 974 SETUP(); 975 masm.UseA32(); 976 START(); 977 978 // Data to compare to `reference`. 979 TestResult* results[ARRAY_SIZE(kTests)]; 980 981 // Test cases for memory bound instructions may allocate a buffer and save its 982 // address in this array. 983 byte* scratch_memory_buffers[ARRAY_SIZE(kTests)]; 984 985 // Generate a loop for each element in `kTests`. Each loop tests one specific 986 // instruction. 987 for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) { 988 // Allocate results on the heap for this test. 989 results[i] = new TestResult; 990 results[i]->outputs = new Inputs[kTests[i].input_size]; 991 results[i]->output_size = kTests[i].input_size; 992 993 size_t input_stride = sizeof(kTests[i].inputs[0]) * kTests[i].input_size; 994 VIXL_ASSERT(IsUint32(input_stride)); 995 996 scratch_memory_buffers[i] = NULL; 997 998 Label loop; 999 UseScratchRegisterScope scratch_registers(&masm); 1000 // Include all registers from r0 ro r12. 1001 scratch_registers.Include(RegisterList(0x1fff)); 1002 1003 // Values to pass to the macro-assembler. 1004 Condition cond = kTests[i].operands.cond; 1005 Register rd = kTests[i].operands.rd; 1006 Register rn = kTests[i].operands.rn; 1007 ShiftType shift = kTests[i].operands.shift; 1008 uint32_t amount = kTests[i].operands.amount; 1009 Operand op(rn, shift, amount); 1010 scratch_registers.Exclude(rd); 1011 scratch_registers.Exclude(rn); 1012 1013 // Allocate reserved registers for our own use. 1014 Register input_ptr = scratch_registers.Acquire(); 1015 Register input_end = scratch_registers.Acquire(); 1016 Register result_ptr = scratch_registers.Acquire(); 1017 1018 // Initialize `input_ptr` to the first element and `input_end` the address 1019 // after the array. 1020 __ Mov(input_ptr, Operand::From(kTests[i].inputs)); 1021 __ Add(input_end, input_ptr, static_cast<uint32_t>(input_stride)); 1022 __ Mov(result_ptr, Operand::From(results[i]->outputs)); 1023 __ Bind(&loop); 1024 1025 { 1026 UseScratchRegisterScope temp_registers(&masm); 1027 Register nzcv_bits = temp_registers.Acquire(); 1028 Register saved_q_bit = temp_registers.Acquire(); 1029 // Save the `Q` bit flag. 1030 __ Mrs(saved_q_bit, APSR); 1031 __ And(saved_q_bit, saved_q_bit, QFlag); 1032 // Set the `NZCV` and `Q` flags together. 1033 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr))); 1034 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); 1035 __ Msr(APSR_nzcvq, nzcv_bits); 1036 } 1037 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd))); 1038 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn))); 1039 1040 (masm.*instruction)(cond, rd, op); 1041 1042 { 1043 UseScratchRegisterScope temp_registers(&masm); 1044 Register nzcv_bits = temp_registers.Acquire(); 1045 __ Mrs(nzcv_bits, APSR); 1046 // Only record the NZCV bits. 1047 __ And(nzcv_bits, nzcv_bits, NZCVFlag); 1048 __ Str(nzcv_bits, MemOperand(result_ptr, offsetof(Inputs, apsr))); 1049 } 1050 __ Str(rd, MemOperand(result_ptr, offsetof(Inputs, rd))); 1051 __ Str(rn, MemOperand(result_ptr, offsetof(Inputs, rn))); 1052 1053 // Advance the result pointer. 1054 __ Add(result_ptr, result_ptr, Operand::From(sizeof(kTests[i].inputs[0]))); 1055 // Loop back until `input_ptr` is lower than `input_base`. 1056 __ Add(input_ptr, input_ptr, Operand::From(sizeof(kTests[i].inputs[0]))); 1057 __ Cmp(input_ptr, input_end); 1058 __ B(ne, &loop); 1059 } 1060 1061 END(); 1062 1063 RUN(); 1064 1065 if (Test::generate_test_trace()) { 1066 // Print the results. 1067 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 1068 printf("static const Inputs kOutputs_%s_%s[] = {\n", 1069 mnemonic, 1070 kTests[i].identifier); 1071 for (size_t j = 0; j < results[i]->output_size; j++) { 1072 printf(" { "); 1073 printf("0x%08" PRIx32, results[i]->outputs[j].apsr); 1074 printf(", "); 1075 printf("0x%08" PRIx32, results[i]->outputs[j].rd); 1076 printf(", "); 1077 printf("0x%08" PRIx32, results[i]->outputs[j].rn); 1078 printf(" },\n"); 1079 } 1080 printf("};\n"); 1081 } 1082 printf("static const TestResult kReference%s[] = {\n", mnemonic); 1083 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 1084 printf(" {\n"); 1085 printf(" ARRAY_SIZE(kOutputs_%s_%s),\n", 1086 mnemonic, 1087 kTests[i].identifier); 1088 printf(" kOutputs_%s_%s,\n", mnemonic, kTests[i].identifier); 1089 printf(" },\n"); 1090 } 1091 printf("};\n"); 1092 } else if (kCheckSimulatorTestResults) { 1093 // Check the results. 1094 unsigned total_error_count = 0; 1095 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 1096 bool instruction_has_errors = false; 1097 for (size_t j = 0; j < kTests[i].input_size; j++) { 1098 uint32_t apsr = results[i]->outputs[j].apsr; 1099 uint32_t rd = results[i]->outputs[j].rd; 1100 uint32_t rn = results[i]->outputs[j].rn; 1101 uint32_t apsr_input = kTests[i].inputs[j].apsr; 1102 uint32_t rd_input = kTests[i].inputs[j].rd; 1103 uint32_t rn_input = kTests[i].inputs[j].rn; 1104 uint32_t apsr_ref = reference[i].outputs[j].apsr; 1105 uint32_t rd_ref = reference[i].outputs[j].rd; 1106 uint32_t rn_ref = reference[i].outputs[j].rn; 1107 1108 if (((apsr != apsr_ref) || (rd != rd_ref) || (rn != rn_ref)) && 1109 (++total_error_count <= kErrorReportLimit)) { 1110 // Print the instruction once even if it triggered multiple failures. 1111 if (!instruction_has_errors) { 1112 printf("Error(s) when testing \"%s %s\":\n", 1113 mnemonic, 1114 kTests[i].operands_description); 1115 instruction_has_errors = true; 1116 } 1117 // Print subsequent errors. 1118 printf(" Input: "); 1119 printf("0x%08" PRIx32, apsr_input); 1120 printf(", "); 1121 printf("0x%08" PRIx32, rd_input); 1122 printf(", "); 1123 printf("0x%08" PRIx32, rn_input); 1124 printf("\n"); 1125 printf(" Expected: "); 1126 printf("0x%08" PRIx32, apsr_ref); 1127 printf(", "); 1128 printf("0x%08" PRIx32, rd_ref); 1129 printf(", "); 1130 printf("0x%08" PRIx32, rn_ref); 1131 printf("\n"); 1132 printf(" Found: "); 1133 printf("0x%08" PRIx32, apsr); 1134 printf(", "); 1135 printf("0x%08" PRIx32, rd); 1136 printf(", "); 1137 printf("0x%08" PRIx32, rn); 1138 printf("\n\n"); 1139 } 1140 } 1141 } 1142 1143 if (total_error_count > kErrorReportLimit) { 1144 printf("%u other errors follow.\n", 1145 total_error_count - kErrorReportLimit); 1146 } 1147 VIXL_CHECK(total_error_count == 0); 1148 } else { 1149 VIXL_WARNING("Assembled the code, but did not run anything.\n"); 1150 } 1151 1152 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 1153 delete[] results[i]->outputs; 1154 delete results[i]; 1155 delete[] scratch_memory_buffers[i]; 1156 } 1157 1158 TEARDOWN(); 1159} 1160 1161// Instantiate tests for each instruction in the list. 1162#define TEST(mnemonic) \ 1163 static void Test_##mnemonic() { \ 1164 TestHelper(&MacroAssembler::mnemonic, #mnemonic, kReference##mnemonic); \ 1165 } \ 1166 static Test test_##mnemonic( \ 1167 "AARCH32_SIMULATOR_COND_RD_OPERAND_RN_SHIFT_AMOUNT_1TO31_" \ 1168 "A32_" #mnemonic, \ 1169 &Test_##mnemonic); 1170FOREACH_INSTRUCTION(TEST) 1171#undef TEST 1172 1173} // aarch32 1174} // vixl 1175