1// Copyright 2014, VIXL authors 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are met: 6// 7// * Redistributions of source code must retain the above copyright notice, 8// this list of conditions and the following disclaimer. 9// * Redistributions in binary form must reproduce the above copyright notice, 10// this list of conditions and the following disclaimer in the documentation 11// and/or other materials provided with the distribution. 12// * Neither the name of ARM Limited nor the names of its contributors may be 13// used to endorse or promote products derived from this software without 14// specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27#include <cstdlib> 28 29#include "test-runner.h" 30 31#include "aarch64/decoder-aarch64.h" 32#include "aarch64/disasm-aarch64.h" 33 34#define TEST(name) TEST_(AARCH64_FUZZ_##name) 35 36 37namespace vixl { 38namespace aarch64 { 39 40 41TEST(decoder) { 42 // Feed noise into the decoder to check that it doesn't crash. 43 // 43 million = ~1% of the instruction space. 44 static const int instruction_count = 43 * 1024 * 1024; 45 46 uint16_t seed[3] = {1, 2, 3}; 47 seed48(seed); 48 49 Decoder decoder; 50 Instruction buffer[kInstructionSize]; 51 52 for (int i = 0; i < instruction_count; i++) { 53 uint32_t instr = static_cast<uint32_t>(mrand48()); 54 buffer->SetInstructionBits(instr); 55 decoder.Decode(buffer); 56 } 57} 58 59TEST(disasm) { 60 // Feed noise into the disassembler to check that it doesn't crash. 61 // 9 million = ~0.2% of the instruction space. 62 static const int instruction_count = 9 * 1024 * 1024; 63 64 uint16_t seed[3] = {42, 43, 44}; 65 seed48(seed); 66 67 Decoder decoder; 68 Disassembler disasm; 69 Instruction buffer[kInstructionSize]; 70 71 decoder.AppendVisitor(&disasm); 72 for (int i = 0; i < instruction_count; i++) { 73 uint32_t instr = static_cast<uint32_t>(mrand48()); 74 buffer->SetInstructionBits(instr); 75 decoder.Decode(buffer); 76 } 77} 78 79#if 0 80// These tests are commented out as they take a long time to run, causing the 81// test script to timeout. After enabling them, they are best run manually: 82// 83// test-runner_sim FUZZ_decoder_pedantic 84// test-runner_sim FUZZ_disasm_pedantic 85// 86// or test-runner_sim_g for debug builds. 87 88TEST(decoder_pedantic) { 89 // Test the entire instruction space. 90 Decoder decoder; 91 Instruction buffer[kInstructionSize]; 92 93 for (uint64_t i = 0; i < (UINT64_C(1) << 32); i++) { 94 if ((i & 0xffffff) == 0) { 95 fprintf(stderr, "0x%08" PRIx32 "\n", static_cast<uint32_t>(i)); 96 } 97 buffer->SetInstructionBits(static_cast<uint32_t>(i)); 98 decoder.Decode(buffer); 99 } 100} 101 102TEST(disasm_pedantic) { 103 // Test the entire instruction space. Warning: takes about 30 minutes on a 104 // high-end CPU. 105 Decoder decoder; 106 PrintDisassembler disasm(stdout); 107 Instruction buffer[kInstructionSize]; 108 109 decoder.AppendVisitor(&disasm); 110 for (uint64_t i = 0; i < (UINT64_C(1) << 32); i++) { 111 if ((i & 0xffff) == 0) { 112 fprintf(stderr, "0x%08" PRIx32 "\n", static_cast<uint32_t>(i)); 113 } 114 buffer->SetInstructionBits(static_cast<uint32_t>(i)); 115 decoder.Decode(buffer); 116 } 117} 118#endif 119 120} // namespace aarch64 121} // namespace vixl 122