1#ifndef _MSM_MDP_H_ 2#define _MSM_MDP_H_ 3 4#include <stdint.h> 5#include <linux/fb.h> 6 7#define MSMFB_IOCTL_MAGIC 'm' 8#define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 9#define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 10#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 11#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 12#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 13#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 14#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 15/* new ioctls's for set/get ccs matrix */ 16#define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 17#define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 18#define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \ 19 struct mdp_overlay) 20#define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 21 22#define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \ 23 struct msmfb_overlay_data) 24#define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 25 26#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \ 27 struct mdp_page_protection) 28#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \ 29 struct mdp_page_protection) 30#define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \ 31 struct mdp_overlay) 32#define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 33#define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \ 34 struct msmfb_overlay_blt) 35#define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 36#define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \ 37 struct mdp_histogram_start_req) 38#define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 39#define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 40 41#define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \ 42 struct msmfb_overlay_3d) 43 44#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \ 45 struct msmfb_mixer_info_req) 46#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \ 47 struct msmfb_overlay_data) 48#define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 49#define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 50#define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 51#define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \ 52 struct msmfb_data) 53#define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \ 54 struct msmfb_data) 55#define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 56#define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 57#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 58#define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 59#define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 60#define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 61#define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \ 62 struct mdp_display_commit) 63#define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 64#define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 65#define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \ 66 unsigned int) 67#define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 68#define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, \ 69 struct mdp_overlay_list) 70#define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) 71#define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, \ 72 struct mdp_pp_feature_version) 73 74#define FB_TYPE_3D_PANEL 0x10101010 75#define MDP_IMGTYPE2_START 0x10000 76#define MSMFB_DRIVER_VERSION 0xF9E8D701 77/* Maximum number of formats supported by MDP*/ 78#define MDP_IMGTYPE_END 0x100 79 80/* HW Revisions for different MDSS targets */ 81#define MDSS_GET_MAJOR(rev) ((rev) >> 28) 82#define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 83#define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 84#define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 85 86#define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2) \ 87 (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 88 89#define MDSS_MDP_REV(major, minor, step) \ 90 ((((major) & 0x000F) << 28) | \ 91 (((minor) & 0x0FFF) << 16) | \ 92 ((step) & 0xFFFF)) 93 94#define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */ 95#define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */ 96#define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */ 97#define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) /* 8926 v2.0 */ 98#define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */ 99#define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */ 100#define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */ 101#define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */ 102#define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */ 103#define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */ 104#define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) /* 8996 v1 */ 105#define MDSS_MDP_HW_REV_107_1 MDSS_MDP_REV(1, 7, 1) /* 8996 v2 */ 106#define MDSS_MDP_HW_REV_107_2 MDSS_MDP_REV(1, 7, 2) /* 8996 v3 */ 107#define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */ 108#define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */ 109#define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) /* 8992 v1.0 */ 110#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */ 111#define MDSS_MDP_HW_REV_112 MDSS_MDP_REV(1, 12, 0) /* 8952 v1.0 */ 112#define MDSS_MDP_HW_REV_114 MDSS_MDP_REV(1, 14, 0) /* 8937 v1.0 */ 113#define MDSS_MDP_HW_REV_115 MDSS_MDP_REV(1, 15, 0) /* msmgold */ 114#define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) /* msmtitanium */ 115#define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) /* msm8998 */ 116#define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) /* msm8998 v1.0 */ 117#define MDSS_MDP_HW_REV_320 MDSS_MDP_REV(3, 2, 0) /* sdm660 */ 118#define MDSS_MDP_HW_REV_330 MDSS_MDP_REV(3, 3, 0) /* sdm630 */ 119 120enum { 121 NOTIFY_UPDATE_INIT, 122 NOTIFY_UPDATE_DEINIT, 123 NOTIFY_UPDATE_START, 124 NOTIFY_UPDATE_STOP, 125 NOTIFY_UPDATE_POWER_OFF, 126}; 127 128enum { 129 NOTIFY_TYPE_NO_UPDATE, 130 NOTIFY_TYPE_SUSPEND, 131 NOTIFY_TYPE_UPDATE, 132 NOTIFY_TYPE_BL_UPDATE, 133 NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, 134}; 135 136enum { 137 MDP_RGB_565, /* RGB 565 planer */ 138 MDP_XRGB_8888, /* RGB 888 padded */ 139 MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */ 140 MDP_Y_CBCR_H2V2_ADRENO, 141 MDP_ARGB_8888, /* ARGB 888 */ 142 MDP_RGB_888, /* RGB 888 planer */ 143 MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */ 144 MDP_YCRYCB_H2V1, /* YCrYCb interleave */ 145 MDP_CBYCRY_H2V1, /* CbYCrY interleave */ 146 MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 147 MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 148 MDP_Y_CRCB_H1V2, 149 MDP_Y_CBCR_H1V2, 150 MDP_RGBA_8888, /* ARGB 888 */ 151 MDP_BGRA_8888, /* ABGR 888 */ 152 MDP_RGBX_8888, /* RGBX 888 */ 153 MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */ 154 MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */ 155 MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */ 156 MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */ 157 MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */ 158 MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 159 MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */ 160 MDP_YCRCB_H1V1, /* YCrCb interleave */ 161 MDP_YCBCR_H1V1, /* YCbCr interleave */ 162 MDP_BGR_565, /* BGR 565 planer */ 163 MDP_BGR_888, /* BGR 888 */ 164 MDP_Y_CBCR_H2V2_VENUS, 165 MDP_BGRX_8888, /* BGRX 8888 */ 166 MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */ 167 MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */ 168 MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */ 169 MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */ 170 MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */ 171 MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */ 172 MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */ 173 MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */ 174 MDP_YCBYCR_H2V1, /* YCbYCr interleave */ 175 MDP_RGB_565_TILE, /* RGB 565 in tile format */ 176 MDP_BGR_565_TILE, /* BGR 565 in tile format */ 177 MDP_ARGB_1555, /*ARGB 1555*/ 178 MDP_RGBA_5551, /*RGBA 5551*/ 179 MDP_ARGB_4444, /*ARGB 4444*/ 180 MDP_RGBA_4444, /*RGBA 4444*/ 181 MDP_RGB_565_UBWC, 182 MDP_RGBA_8888_UBWC, 183 MDP_Y_CBCR_H2V2_UBWC, 184 MDP_RGBX_8888_UBWC, 185 MDP_Y_CRCB_H2V2_VENUS, 186 MDP_IMGTYPE_LIMIT, 187 MDP_RGB_BORDERFILL, /* border fill pipe */ 188 MDP_XRGB_1555, 189 MDP_RGBX_5551, 190 MDP_XRGB_4444, 191 MDP_RGBX_4444, 192 MDP_ABGR_1555, 193 MDP_BGRA_5551, 194 MDP_XBGR_1555, 195 MDP_BGRX_5551, 196 MDP_ABGR_4444, 197 MDP_BGRA_4444, 198 MDP_XBGR_4444, 199 MDP_BGRX_4444, 200 MDP_ABGR_8888, 201 MDP_XBGR_8888, 202 MDP_RGBA_1010102, 203 MDP_ARGB_2101010, 204 MDP_RGBX_1010102, 205 MDP_XRGB_2101010, 206 MDP_BGRA_1010102, 207 MDP_ABGR_2101010, 208 MDP_BGRX_1010102, 209 MDP_XBGR_2101010, 210 MDP_RGBA_1010102_UBWC, 211 MDP_RGBX_1010102_UBWC, 212 MDP_Y_CBCR_H2V2_P010, 213 MDP_Y_CBCR_H2V2_TP10_UBWC, 214 MDP_CRYCBY_H2V1, /* CrYCbY interleave */ 215 MDP_IMGTYPE_LIMIT1 = MDP_IMGTYPE_END, 216 MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */ 217 MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */ 218}; 219 220#define MDP_CRYCBY_H2V1 MDP_CRYCBY_H2V1 221 222enum { 223 PMEM_IMG, 224 FB_IMG, 225}; 226 227enum { 228 HSIC_HUE = 0, 229 HSIC_SAT, 230 HSIC_INT, 231 HSIC_CON, 232 NUM_HSIC_PARAM, 233}; 234 235enum mdss_mdp_max_bw_mode { 236 MDSS_MAX_BW_LIMIT_DEFAULT = 0x1, 237 MDSS_MAX_BW_LIMIT_CAMERA = 0x2, 238 MDSS_MAX_BW_LIMIT_HFLIP = 0x4, 239 MDSS_MAX_BW_LIMIT_VFLIP = 0x8, 240}; 241 242#define MDSS_MDP_ROT_ONLY 0x80 243#define MDSS_MDP_RIGHT_MIXER 0x100 244#define MDSS_MDP_DUAL_PIPE 0x200 245 246/* mdp_blit_req flag values */ 247#define MDP_ROT_NOP 0 248#define MDP_FLIP_LR 0x1 249#define MDP_FLIP_UD 0x2 250#define MDP_ROT_90 0x4 251#define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) 252#define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) 253#define MDP_DITHER 0x8 254#define MDP_BLUR 0x10 255#define MDP_BLEND_FG_PREMULT 0x20000 256#define MDP_IS_FG 0x40000 257#define MDP_SOLID_FILL 0x00000020 258#define MDP_VPU_PIPE 0x00000040 259#define MDP_DEINTERLACE 0x80000000 260#define MDP_SHARPENING 0x40000000 261#define MDP_NO_DMA_BARRIER_START 0x20000000 262#define MDP_NO_DMA_BARRIER_END 0x10000000 263#define MDP_NO_BLIT 0x08000000 264#define MDP_BLIT_WITH_DMA_BARRIERS 0x000 265#define MDP_BLIT_WITH_NO_DMA_BARRIERS \ 266 (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 267#define MDP_BLIT_SRC_GEM 0x04000000 268#define MDP_BLIT_DST_GEM 0x02000000 269#define MDP_BLIT_NON_CACHED 0x01000000 270#define MDP_OV_PIPE_SHARE 0x00800000 271#define MDP_DEINTERLACE_ODD 0x00400000 272#define MDP_OV_PLAY_NOWAIT 0x00200000 273#define MDP_SOURCE_ROTATED_90 0x00100000 274#define MDP_OVERLAY_PP_CFG_EN 0x00080000 275#define MDP_BACKEND_COMPOSITION 0x00040000 276#define MDP_BORDERFILL_SUPPORTED 0x00010000 277#define MDP_SECURE_OVERLAY_SESSION 0x00008000 278#define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 279#define MDP_OV_PIPE_FORCE_DMA 0x00004000 280#define MDP_MEMORY_ID_TYPE_FB 0x00001000 281#define MDP_BWC_EN 0x00000400 282#define MDP_DECIMATION_EN 0x00000800 283#define MDP_SMP_FORCE_ALLOC 0x00200000 284#define MDP_TRANSP_NOP 0xffffffff 285#define MDP_ALPHA_NOP 0xff 286 287#define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 288#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 289#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 290#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 291#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 292/* Sentinel: Don't use! */ 293#define MDP_FB_PAGE_PROTECTION_INVALID (5) 294/* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */ 295#define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 296 297#define MDP_DEEP_COLOR_YUV444 0x1 298#define MDP_DEEP_COLOR_RGB30B 0x2 299#define MDP_DEEP_COLOR_RGB36B 0x4 300#define MDP_DEEP_COLOR_RGB48B 0x8 301 302struct mdp_rect { 303 uint32_t x; 304 uint32_t y; 305 uint32_t w; 306 uint32_t h; 307}; 308 309struct mdp_img { 310 uint32_t width; 311 uint32_t height; 312 uint32_t format; 313 uint32_t offset; 314 int memory_id; /* the file descriptor */ 315 uint32_t priv; 316}; 317 318struct mult_factor { 319 uint32_t numer; 320 uint32_t denom; 321}; 322 323/* 324 * {3x3} + {3} ccs matrix 325 */ 326 327#define MDP_CCS_RGB2YUV 0 328#define MDP_CCS_YUV2RGB 1 329 330#define MDP_CCS_SIZE 9 331#define MDP_BV_SIZE 3 332 333struct mdp_ccs { 334 int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */ 335 uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */ 336 uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */ 337}; 338 339struct mdp_csc { 340 int id; 341 uint32_t csc_mv[9]; 342 uint32_t csc_pre_bv[3]; 343 uint32_t csc_post_bv[3]; 344 uint32_t csc_pre_lv[6]; 345 uint32_t csc_post_lv[6]; 346}; 347 348/* The version of the mdp_blit_req structure so that 349 * user applications can selectively decide which functionality 350 * to include 351 */ 352 353#define MDP_BLIT_REQ_VERSION 3 354 355struct color { 356 uint32_t r; 357 uint32_t g; 358 uint32_t b; 359 uint32_t alpha; 360}; 361 362struct mdp_blit_req { 363 struct mdp_img src; 364 struct mdp_img dst; 365 struct mdp_rect src_rect; 366 struct mdp_rect dst_rect; 367 struct color const_color; 368 uint32_t alpha; 369 uint32_t transp_mask; 370 uint32_t flags; 371 int sharpening_strength; /* -127 <--> 127, default 64 */ 372 uint8_t color_space; 373 uint32_t fps; 374}; 375 376struct mdp_blit_req_list { 377 uint32_t count; 378 struct mdp_blit_req req[]; 379}; 380 381#define MSMFB_DATA_VERSION 2 382 383struct msmfb_data { 384 uint32_t offset; 385 int memory_id; 386 int id; 387 uint32_t flags; 388 uint32_t priv; 389 uint32_t iova; 390}; 391 392#define MSMFB_NEW_REQUEST -1 393 394struct msmfb_overlay_data { 395 uint32_t id; 396 struct msmfb_data data; 397 uint32_t version_key; 398 struct msmfb_data plane1_data; 399 struct msmfb_data plane2_data; 400 struct msmfb_data dst_data; 401}; 402 403struct msmfb_img { 404 uint32_t width; 405 uint32_t height; 406 uint32_t format; 407}; 408 409#define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 410struct msmfb_writeback_data { 411 struct msmfb_data buf_info; 412 struct msmfb_img img; 413}; 414 415#define MDP_PP_OPS_ENABLE 0x1 416#define MDP_PP_OPS_READ 0x2 417#define MDP_PP_OPS_WRITE 0x4 418#define MDP_PP_OPS_DISABLE 0x8 419#define MDP_PP_IGC_FLAG_ROM0 0x10 420#define MDP_PP_IGC_FLAG_ROM1 0x20 421 422 423#define MDSS_PP_DSPP_CFG 0x000 424#define MDSS_PP_SSPP_CFG 0x100 425#define MDSS_PP_LM_CFG 0x200 426#define MDSS_PP_WB_CFG 0x300 427 428#define MDSS_PP_ARG_MASK 0x3C00 429#define MDSS_PP_ARG_NUM 4 430#define MDSS_PP_ARG_SHIFT 10 431#define MDSS_PP_LOCATION_MASK 0x0300 432#define MDSS_PP_LOGICAL_MASK 0x00FF 433 434#define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 435#define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 436#define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 437#define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 438 439 440struct mdp_qseed_cfg { 441 uint32_t table_num; 442 uint32_t ops; 443 uint32_t len; 444 uint32_t *data; 445}; 446 447struct mdp_sharp_cfg { 448 uint32_t flags; 449 uint32_t strength; 450 uint32_t edge_thr; 451 uint32_t smooth_thr; 452 uint32_t noise_thr; 453}; 454 455struct mdp_qseed_cfg_data { 456 uint32_t block; 457 struct mdp_qseed_cfg qseed_data; 458}; 459 460#define MDP_OVERLAY_PP_CSC_CFG 0x1 461#define MDP_OVERLAY_PP_QSEED_CFG 0x2 462#define MDP_OVERLAY_PP_PA_CFG 0x4 463#define MDP_OVERLAY_PP_IGC_CFG 0x8 464#define MDP_OVERLAY_PP_SHARP_CFG 0x10 465#define MDP_OVERLAY_PP_HIST_CFG 0x20 466#define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 467#define MDP_OVERLAY_PP_PA_V2_CFG 0x80 468#define MDP_OVERLAY_PP_PCC_CFG 0x100 469 470#define MDP_CSC_FLAG_ENABLE 0x1 471#define MDP_CSC_FLAG_YUV_IN 0x2 472#define MDP_CSC_FLAG_YUV_OUT 0x4 473 474#define MDP_CSC_MATRIX_COEFF_SIZE 9 475#define MDP_CSC_CLAMP_SIZE 6 476#define MDP_CSC_BIAS_SIZE 3 477 478struct mdp_csc_cfg { 479 /* flags for enable CSC, toggling RGB,YUV input/output */ 480 uint32_t flags; 481 uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE]; 482 uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE]; 483 uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE]; 484 uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE]; 485 uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE]; 486}; 487 488struct mdp_csc_cfg_data { 489 uint32_t block; 490 struct mdp_csc_cfg csc_data; 491}; 492 493struct mdp_pa_cfg { 494 uint32_t flags; 495 uint32_t hue_adj; 496 uint32_t sat_adj; 497 uint32_t val_adj; 498 uint32_t cont_adj; 499}; 500 501struct mdp_pa_mem_col_cfg { 502 uint32_t color_adjust_p0; 503 uint32_t color_adjust_p1; 504 uint32_t hue_region; 505 uint32_t sat_region; 506 uint32_t val_region; 507}; 508 509#define MDP_SIX_ZONE_LUT_SIZE 384 510 511/* PA Write/Read extension flags */ 512#define MDP_PP_PA_HUE_ENABLE 0x10 513#define MDP_PP_PA_SAT_ENABLE 0x20 514#define MDP_PP_PA_VAL_ENABLE 0x40 515#define MDP_PP_PA_CONT_ENABLE 0x80 516#define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 517#define MDP_PP_PA_SKIN_ENABLE 0x200 518#define MDP_PP_PA_SKY_ENABLE 0x400 519#define MDP_PP_PA_FOL_ENABLE 0x800 520 521/* PA masks */ 522/* Masks used in PA v1_7 only */ 523#define MDP_PP_PA_MEM_PROT_HUE_EN 0x1 524#define MDP_PP_PA_MEM_PROT_SAT_EN 0x2 525#define MDP_PP_PA_MEM_PROT_VAL_EN 0x4 526#define MDP_PP_PA_MEM_PROT_CONT_EN 0x8 527#define MDP_PP_PA_MEM_PROT_SIX_EN 0x10 528#define MDP_PP_PA_MEM_PROT_BLEND_EN 0x20 529/* Masks used in all PAv2 versions */ 530#define MDP_PP_PA_HUE_MASK 0x1000 531#define MDP_PP_PA_SAT_MASK 0x2000 532#define MDP_PP_PA_VAL_MASK 0x4000 533#define MDP_PP_PA_CONT_MASK 0x8000 534#define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 535#define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 536#define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 537#define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 538#define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 539#define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 540#define MDP_PP_PA_MEM_PROTECT_EN 0x400000 541#define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 542 543/* Flags for setting PA saturation and value hold */ 544#define MDP_PP_PA_LEFT_HOLD 0x1 545#define MDP_PP_PA_RIGHT_HOLD 0x2 546 547struct mdp_pa_v2_data { 548 /* Mask bits for PA features */ 549 uint32_t flags; 550 uint32_t global_hue_adj; 551 uint32_t global_sat_adj; 552 uint32_t global_val_adj; 553 uint32_t global_cont_adj; 554 struct mdp_pa_mem_col_cfg skin_cfg; 555 struct mdp_pa_mem_col_cfg sky_cfg; 556 struct mdp_pa_mem_col_cfg fol_cfg; 557 uint32_t six_zone_len; 558 uint32_t six_zone_thresh; 559 uint32_t *six_zone_curve_p0; 560 uint32_t *six_zone_curve_p1; 561}; 562 563struct mdp_pa_mem_col_data_v1_7 { 564 uint32_t color_adjust_p0; 565 uint32_t color_adjust_p1; 566 uint32_t color_adjust_p2; 567 uint32_t blend_gain; 568 uint8_t sat_hold; 569 uint8_t val_hold; 570 uint32_t hue_region; 571 uint32_t sat_region; 572 uint32_t val_region; 573}; 574 575struct mdp_pa_data_v1_7 { 576 uint32_t mode; 577 uint32_t global_hue_adj; 578 uint32_t global_sat_adj; 579 uint32_t global_val_adj; 580 uint32_t global_cont_adj; 581 struct mdp_pa_mem_col_data_v1_7 skin_cfg; 582 struct mdp_pa_mem_col_data_v1_7 sky_cfg; 583 struct mdp_pa_mem_col_data_v1_7 fol_cfg; 584 uint32_t six_zone_thresh; 585 uint32_t six_zone_adj_p0; 586 uint32_t six_zone_adj_p1; 587 uint8_t six_zone_sat_hold; 588 uint8_t six_zone_val_hold; 589 uint32_t six_zone_len; 590 uint32_t *six_zone_curve_p0; 591 uint32_t *six_zone_curve_p1; 592}; 593 594 595struct mdp_pa_v2_cfg_data { 596 uint32_t version; 597 uint32_t block; 598 uint32_t flags; 599 struct mdp_pa_v2_data pa_v2_data; 600 void *cfg_payload; 601}; 602 603 604enum { 605 mdp_igc_rec601 = 1, 606 mdp_igc_rec709, 607 mdp_igc_srgb, 608 mdp_igc_custom, 609 mdp_igc_rec_max, 610}; 611 612struct mdp_igc_lut_data { 613 uint32_t block; 614 uint32_t version; 615 uint32_t len, ops; 616 uint32_t *c0_c1_data; 617 uint32_t *c2_data; 618 void *cfg_payload; 619}; 620 621struct mdp_igc_lut_data_v1_7 { 622 uint32_t table_fmt; 623 uint32_t len; 624 uint32_t *c0_c1_data; 625 uint32_t *c2_data; 626}; 627 628struct mdp_igc_lut_data_payload { 629 uint32_t table_fmt; 630 uint32_t len; 631 uint64_t c0_c1_data; 632 uint64_t c2_data; 633 uint32_t strength; 634}; 635 636struct mdp_histogram_cfg { 637 uint32_t ops; 638 uint32_t block; 639 uint8_t frame_cnt; 640 uint8_t bit_mask; 641 uint16_t num_bins; 642}; 643 644struct mdp_hist_lut_data_v1_7 { 645 uint32_t len; 646 uint32_t *data; 647}; 648 649struct mdp_hist_lut_data { 650 uint32_t block; 651 uint32_t version; 652 uint32_t hist_lut_first; 653 uint32_t ops; 654 uint32_t len; 655 uint32_t *data; 656 void *cfg_payload; 657}; 658 659struct mdp_pcc_coeff { 660 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 661}; 662 663struct mdp_pcc_coeff_v1_7 { 664 uint32_t c, r, g, b, rg, gb, rb, rgb; 665}; 666 667struct mdp_pcc_data_v1_7 { 668 struct mdp_pcc_coeff_v1_7 r, g, b; 669}; 670 671struct mdp_pcc_cfg_data { 672 uint32_t version; 673 uint32_t block; 674 uint32_t ops; 675 struct mdp_pcc_coeff r, g, b; 676 void *cfg_payload; 677}; 678 679enum { 680 mdp_lut_igc, 681 mdp_lut_pgc, 682 mdp_lut_hist, 683 mdp_lut_rgb, 684 mdp_lut_max, 685}; 686struct mdp_overlay_pp_params { 687 uint32_t config_ops; 688 struct mdp_csc_cfg csc_cfg; 689 struct mdp_qseed_cfg qseed_cfg[2]; 690 struct mdp_pa_cfg pa_cfg; 691 struct mdp_pa_v2_data pa_v2_cfg; 692 struct mdp_igc_lut_data igc_cfg; 693 struct mdp_sharp_cfg sharp_cfg; 694 struct mdp_histogram_cfg hist_cfg; 695 struct mdp_hist_lut_data hist_lut_cfg; 696 /* PAv2 cfg data for PA 2.x versions */ 697 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 698 struct mdp_pcc_cfg_data pcc_cfg_data; 699}; 700 701/** 702 * enum mdss_mdp_blend_op - Different blend operations set by userspace 703 * 704 * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. 705 * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer 706 * would appear opaque in case fg plane alpha is 707 * 0xff. 708 * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has 709 * alpha pre-multiplication done. If fg plane alpha 710 * is less than 0xff, apply modulation as well. This 711 * operation is intended on layers having alpha 712 * channel. 713 * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha 714 * pre-multiplied. Apply pre-multiplication. If fg 715 * plane alpha is less than 0xff, apply modulation as 716 * well. 717 * @BLEND_OP_MAX: Used to track maximum blend operation possible by 718 * mdp. 719 */ 720enum mdss_mdp_blend_op { 721 BLEND_OP_NOT_DEFINED = 0, 722 BLEND_OP_OPAQUE, 723 BLEND_OP_PREMULTIPLIED, 724 BLEND_OP_COVERAGE, 725 BLEND_OP_MAX, 726}; 727 728#define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 729#define MAX_PLANES 4 730struct mdp_scale_data { 731 uint8_t enable_pxl_ext; 732 733 int init_phase_x[MAX_PLANES]; 734 int phase_step_x[MAX_PLANES]; 735 int init_phase_y[MAX_PLANES]; 736 int phase_step_y[MAX_PLANES]; 737 738 int num_ext_pxls_left[MAX_PLANES]; 739 int num_ext_pxls_right[MAX_PLANES]; 740 int num_ext_pxls_top[MAX_PLANES]; 741 int num_ext_pxls_btm[MAX_PLANES]; 742 743 int left_ftch[MAX_PLANES]; 744 int left_rpt[MAX_PLANES]; 745 int right_ftch[MAX_PLANES]; 746 int right_rpt[MAX_PLANES]; 747 748 int top_rpt[MAX_PLANES]; 749 int btm_rpt[MAX_PLANES]; 750 int top_ftch[MAX_PLANES]; 751 int btm_ftch[MAX_PLANES]; 752 753 uint32_t roi_w[MAX_PLANES]; 754}; 755 756/** 757 * enum mdp_overlay_pipe_type - Different pipe type set by userspace 758 * 759 * @PIPE_TYPE_AUTO: Not specified, pipe will be selected according to flags. 760 * @PIPE_TYPE_VIG: VIG pipe. 761 * @PIPE_TYPE_RGB: RGB pipe. 762 * @PIPE_TYPE_DMA: DMA pipe. 763 * @PIPE_TYPE_CURSOR: CURSOR pipe. 764 * @PIPE_TYPE_MAX: Used to track maximum number of pipe type. 765 */ 766enum mdp_overlay_pipe_type { 767 PIPE_TYPE_AUTO = 0, 768 PIPE_TYPE_VIG, 769 PIPE_TYPE_RGB, 770 PIPE_TYPE_DMA, 771 PIPE_TYPE_CURSOR, 772 PIPE_TYPE_MAX, 773}; 774 775/** 776 * struct mdp_overlay - overlay surface structure 777 * @src: Source image information (width, height, format). 778 * @src_rect: Source crop rectangle, portion of image that will be fetched. 779 * This should always be within boundaries of source image. 780 * @dst_rect: Destination rectangle, the position and size of image on screen. 781 * This should always be within panel boundaries. 782 * @z_order: Blending stage to occupy in display, if multiple layers are 783 * present, highest z_order usually means the top most visible 784 * layer. The range acceptable is from 0-3 to support blending 785 * up to 4 layers. 786 * @is_fg: This flag is used to disable blending of any layers with z_order 787 * less than this overlay. It means that any layers with z_order 788 * less than this layer will not be blended and will be replaced 789 * by the background border color. 790 * @alpha: Used to set plane opacity. The range can be from 0-255, where 791 * 0 means completely transparent and 255 means fully opaque. 792 * @transp_mask: Color used as color key for transparency. Any pixel in fetched 793 * image matching this color will be transparent when blending. 794 * The color should be in same format as the source image format. 795 * @flags: This is used to customize operation of overlay. See MDP flags 796 * for more information. 797 * @pipe_type: Used to specify the type of overlay pipe. 798 * @user_data: DEPRECATED* Used to store user application specific information. 799 * @bg_color: Solid color used to fill the overlay surface when no source 800 * buffer is provided. 801 * @horz_deci: Horizontal decimation value, this indicates the amount of pixels 802 * dropped for each pixel that is fetched from a line. The value 803 * given should be power of two of decimation amount. 804 * 0: no decimation 805 * 1: decimate by 2 (drop 1 pixel for each pixel fetched) 806 * 2: decimate by 4 (drop 3 pixels for each pixel fetched) 807 * 3: decimate by 8 (drop 7 pixels for each pixel fetched) 808 * 4: decimate by 16 (drop 15 pixels for each pixel fetched) 809 * @vert_deci: Vertical decimation value, this indicates the amount of lines 810 * dropped for each line that is fetched from overlay. The value 811 * given should be power of two of decimation amount. 812 * 0: no decimation 813 * 1: decimation by 2 (drop 1 line for each line fetched) 814 * 2: decimation by 4 (drop 3 lines for each line fetched) 815 * 3: decimation by 8 (drop 7 lines for each line fetched) 816 * 4: decimation by 16 (drop 15 lines for each line fetched) 817 * @overlay_pp_cfg: Overlay post processing configuration, for more information 818 * see struct mdp_overlay_pp_params. 819 * @priority: Priority is returned by the driver when overlay is set for the 820 * first time. It indicates the priority of the underlying pipe 821 * serving the overlay. This priority can be used by user-space 822 * in source split when pipes are re-used and shuffled around to 823 * reduce fallbacks. 824 */ 825struct mdp_overlay { 826 struct msmfb_img src; 827 struct mdp_rect src_rect; 828 struct mdp_rect dst_rect; 829 uint32_t z_order; /* stage number */ 830 uint32_t is_fg; /* control alpha & transp */ 831 uint32_t alpha; 832 uint32_t blend_op; 833 uint32_t transp_mask; 834 uint32_t flags; 835 uint32_t pipe_type; 836 uint32_t id; 837 uint8_t priority; 838 uint32_t user_data[6]; 839 uint32_t bg_color; 840 uint8_t horz_deci; 841 uint8_t vert_deci; 842 struct mdp_overlay_pp_params overlay_pp_cfg; 843 struct mdp_scale_data scale; 844 uint8_t color_space; 845 uint32_t frame_rate; 846}; 847 848struct msmfb_overlay_3d { 849 uint32_t is_3d; 850 uint32_t width; 851 uint32_t height; 852}; 853 854 855struct msmfb_overlay_blt { 856 uint32_t enable; 857 uint32_t offset; 858 uint32_t width; 859 uint32_t height; 860 uint32_t bpp; 861}; 862 863struct mdp_histogram { 864 uint32_t frame_cnt; 865 uint32_t bin_cnt; 866 uint32_t *r; 867 uint32_t *g; 868 uint32_t *b; 869}; 870 871#define MISR_CRC_BATCH_SIZE 32 872enum { 873 DISPLAY_MISR_EDP, 874 DISPLAY_MISR_DSI0, 875 DISPLAY_MISR_DSI1, 876 DISPLAY_MISR_HDMI, 877 DISPLAY_MISR_LCDC, 878 DISPLAY_MISR_MDP, 879 DISPLAY_MISR_ATV, 880 DISPLAY_MISR_DSI_CMD, 881 DISPLAY_MISR_MAX 882}; 883 884enum { 885 MISR_OP_NONE, 886 MISR_OP_SFM, 887 MISR_OP_MFM, 888 MISR_OP_BM, 889 MISR_OP_MAX 890}; 891 892struct mdp_misr { 893 uint32_t block_id; 894 uint32_t frame_count; 895 uint32_t crc_op_mode; 896 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 897}; 898 899/* 900 901 mdp_block_type defines the identifiers for pipes in MDP 4.3 and up 902 903 MDP_BLOCK_RESERVED is provided for backward compatibility and is 904 deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used 905 instead. 906 907 MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses, 908 same for others. 909 910*/ 911 912enum { 913 MDP_BLOCK_RESERVED = 0, 914 MDP_BLOCK_OVERLAY_0, 915 MDP_BLOCK_OVERLAY_1, 916 MDP_BLOCK_VG_1, 917 MDP_BLOCK_VG_2, 918 MDP_BLOCK_RGB_1, 919 MDP_BLOCK_RGB_2, 920 MDP_BLOCK_DMA_P, 921 MDP_BLOCK_DMA_S, 922 MDP_BLOCK_DMA_E, 923 MDP_BLOCK_OVERLAY_2, 924 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 925 MDP_LOGICAL_BLOCK_DISP_1, 926 MDP_LOGICAL_BLOCK_DISP_2, 927 MDP_BLOCK_MAX, 928}; 929 930/* 931 * mdp_histogram_start_req is used to provide the parameters for 932 * histogram start request 933 */ 934 935struct mdp_histogram_start_req { 936 uint32_t block; 937 uint8_t frame_cnt; 938 uint8_t bit_mask; 939 uint16_t num_bins; 940}; 941 942/* 943 * mdp_histogram_data is used to return the histogram data, once 944 * the histogram is done/stopped/cance 945 */ 946 947struct mdp_histogram_data { 948 uint32_t block; 949 uint32_t bin_cnt; 950 uint32_t *c0; 951 uint32_t *c1; 952 uint32_t *c2; 953 uint32_t *extra_info; 954}; 955 956 957#define GC_LUT_ENTRIES_V1_7 512 958 959struct mdp_ar_gc_lut_data { 960 uint32_t x_start; 961 uint32_t slope; 962 uint32_t offset; 963}; 964 965#define MDP_PP_PGC_ROUNDING_ENABLE 0x10 966struct mdp_pgc_lut_data { 967 uint32_t version; 968 uint32_t block; 969 uint32_t flags; 970 uint8_t num_r_stages; 971 uint8_t num_g_stages; 972 uint8_t num_b_stages; 973 struct mdp_ar_gc_lut_data *r_data; 974 struct mdp_ar_gc_lut_data *g_data; 975 struct mdp_ar_gc_lut_data *b_data; 976 void *cfg_payload; 977}; 978 979#define PGC_LUT_ENTRIES 1024 980struct mdp_pgc_lut_data_v1_7 { 981 uint32_t len; 982 uint32_t *c0_data; 983 uint32_t *c1_data; 984 uint32_t *c2_data; 985}; 986 987/* 988 * mdp_rgb_lut_data is used to provide parameters for configuring the 989 * generic RGB lut in case of gamma correction or other LUT updation usecases 990 */ 991struct mdp_rgb_lut_data { 992 uint32_t flags; 993 uint32_t lut_type; 994 struct fb_cmap cmap; 995}; 996 997enum { 998 mdp_rgb_lut_gc, 999 mdp_rgb_lut_hist, 1000}; 1001 1002struct mdp_lut_cfg_data { 1003 uint32_t lut_type; 1004 union { 1005 struct mdp_igc_lut_data igc_lut_data; 1006 struct mdp_pgc_lut_data pgc_lut_data; 1007 struct mdp_hist_lut_data hist_lut_data; 1008 struct mdp_rgb_lut_data rgb_lut_data; 1009 } data; 1010}; 1011 1012struct mdp_bl_scale_data { 1013 uint32_t min_lvl; 1014 uint32_t scale; 1015}; 1016 1017struct mdp_pa_cfg_data { 1018 uint32_t block; 1019 struct mdp_pa_cfg pa_data; 1020}; 1021 1022#define MDP_DITHER_DATA_V1_7_SZ 16 1023 1024struct mdp_dither_data_v1_7 { 1025 uint32_t g_y_depth; 1026 uint32_t r_cr_depth; 1027 uint32_t b_cb_depth; 1028 uint32_t len; 1029 uint32_t data[MDP_DITHER_DATA_V1_7_SZ]; 1030 uint32_t temporal_en; 1031}; 1032 1033struct mdp_pa_dither_data { 1034 uint64_t data_flags; 1035 uint32_t matrix_sz; 1036 uint64_t matrix_data; 1037 uint32_t strength; 1038 uint32_t offset_en; 1039}; 1040 1041struct mdp_dither_cfg_data { 1042 uint32_t version; 1043 uint32_t block; 1044 uint32_t flags; 1045 uint32_t mode; 1046 uint32_t g_y_depth; 1047 uint32_t r_cr_depth; 1048 uint32_t b_cb_depth; 1049 void *cfg_payload; 1050}; 1051 1052#define MDP_GAMUT_TABLE_NUM 8 1053#define MDP_GAMUT_TABLE_NUM_V1_7 4 1054#define MDP_GAMUT_SCALE_OFF_TABLE_NUM 3 1055#define MDP_GAMUT_TABLE_V1_7_SZ 1229 1056#define MDP_GAMUT_SCALE_OFF_SZ 16 1057#define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32 1058 1059struct mdp_gamut_cfg_data { 1060 uint32_t block; 1061 uint32_t flags; 1062 uint32_t version; 1063 /* v1 version specific params */ 1064 uint32_t gamut_first; 1065 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 1066 uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM]; 1067 uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM]; 1068 uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM]; 1069 /* params for newer versions of gamut */ 1070 void *cfg_payload; 1071}; 1072 1073enum { 1074 mdp_gamut_fine_mode = 0x1, 1075 mdp_gamut_coarse_mode, 1076}; 1077 1078struct mdp_gamut_data_v1_7 { 1079 uint32_t mode; 1080 uint32_t map_en; 1081 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7]; 1082 uint32_t *c0_data[MDP_GAMUT_TABLE_NUM_V1_7]; 1083 uint32_t *c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7]; 1084 uint32_t tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 1085 uint32_t *scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 1086}; 1087 1088struct mdp_calib_config_data { 1089 uint32_t ops; 1090 uint32_t addr; 1091 uint32_t data; 1092}; 1093 1094struct mdp_calib_config_buffer { 1095 uint32_t ops; 1096 uint32_t size; 1097 uint32_t *buffer; 1098}; 1099 1100struct mdp_calib_dcm_state { 1101 uint32_t ops; 1102 uint32_t dcm_state; 1103}; 1104 1105enum { 1106 DCM_UNINIT, 1107 DCM_UNBLANK, 1108 DCM_ENTER, 1109 DCM_EXIT, 1110 DCM_BLANK, 1111 DTM_ENTER, 1112 DTM_EXIT, 1113}; 1114 1115#define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 1116#define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 1117#define MDSS_PP_SPLIT_MASK 0x30000000 1118 1119#define MDSS_MAX_BL_BRIGHTNESS 255 1120#define AD_BL_LIN_LEN 256 1121#define AD_BL_ATT_LUT_LEN 33 1122 1123#define MDSS_AD_MODE_AUTO_BL 0x0 1124#define MDSS_AD_MODE_AUTO_STR 0x1 1125#define MDSS_AD_MODE_TARG_STR 0x3 1126#define MDSS_AD_MODE_MAN_STR 0x7 1127#define MDSS_AD_MODE_CALIB 0xF 1128 1129#define MDP_PP_AD_INIT 0x10 1130#define MDP_PP_AD_CFG 0x20 1131 1132struct mdss_ad_init { 1133 uint32_t asym_lut[33]; 1134 uint32_t color_corr_lut[33]; 1135 uint8_t i_control[2]; 1136 uint16_t black_lvl; 1137 uint16_t white_lvl; 1138 uint8_t var; 1139 uint8_t limit_ampl; 1140 uint8_t i_dither; 1141 uint8_t slope_max; 1142 uint8_t slope_min; 1143 uint8_t dither_ctl; 1144 uint8_t format; 1145 uint8_t auto_size; 1146 uint16_t frame_w; 1147 uint16_t frame_h; 1148 uint8_t logo_v; 1149 uint8_t logo_h; 1150 uint32_t alpha; 1151 uint32_t alpha_base; 1152 uint32_t al_thresh; 1153 uint32_t bl_lin_len; 1154 uint32_t bl_att_len; 1155 uint32_t *bl_lin; 1156 uint32_t *bl_lin_inv; 1157 uint32_t *bl_att_lut; 1158}; 1159 1160#define MDSS_AD_BL_CTRL_MODE_EN 1 1161#define MDSS_AD_BL_CTRL_MODE_DIS 0 1162struct mdss_ad_cfg { 1163 uint32_t mode; 1164 uint32_t al_calib_lut[33]; 1165 uint16_t backlight_min; 1166 uint16_t backlight_max; 1167 uint16_t backlight_scale; 1168 uint16_t amb_light_min; 1169 uint16_t filter[2]; 1170 uint16_t calib[4]; 1171 uint8_t strength_limit; 1172 uint8_t t_filter_recursion; 1173 uint16_t stab_itr; 1174 uint32_t bl_ctrl_mode; 1175}; 1176 1177struct mdss_ad_bl_cfg { 1178 uint32_t bl_min_delta; 1179 uint32_t bl_low_limit; 1180}; 1181 1182/* ops uses standard MDP_PP_* flags */ 1183struct mdss_ad_init_cfg { 1184 uint32_t ops; 1185 union { 1186 struct mdss_ad_init init; 1187 struct mdss_ad_cfg cfg; 1188 } params; 1189}; 1190 1191/* mode uses MDSS_AD_MODE_* flags */ 1192struct mdss_ad_input { 1193 uint32_t mode; 1194 union { 1195 uint32_t amb_light; 1196 uint32_t strength; 1197 uint32_t calib_bl; 1198 } in; 1199 uint32_t output; 1200}; 1201 1202#define MDSS_CALIB_MODE_BL 0x1 1203struct mdss_calib_cfg { 1204 uint32_t ops; 1205 uint32_t calib_mask; 1206}; 1207 1208enum { 1209 mdp_op_pcc_cfg, 1210 mdp_op_csc_cfg, 1211 mdp_op_lut_cfg, 1212 mdp_op_qseed_cfg, 1213 mdp_bl_scale_cfg, 1214 mdp_op_pa_cfg, 1215 mdp_op_pa_v2_cfg, 1216 mdp_op_dither_cfg, 1217 mdp_op_gamut_cfg, 1218 mdp_op_calib_cfg, 1219 mdp_op_ad_cfg, 1220 mdp_op_ad_input, 1221 mdp_op_calib_mode, 1222 mdp_op_calib_buffer, 1223 mdp_op_calib_dcm_state, 1224 mdp_op_max, 1225 mdp_op_pa_dither_cfg, 1226 mdp_op_ad_bl_cfg, 1227 mdp_op_pp_max = 255, 1228}; 1229#define mdp_op_pa_dither_cfg mdp_op_pa_dither_cfg 1230#define mdp_op_pp_max mdp_op_pp_max 1231 1232#define mdp_op_ad_bl_cfg mdp_op_ad_bl_cfg 1233 1234enum { 1235 WB_FORMAT_NV12, 1236 WB_FORMAT_RGB_565, 1237 WB_FORMAT_RGB_888, 1238 WB_FORMAT_xRGB_8888, 1239 WB_FORMAT_ARGB_8888, 1240 WB_FORMAT_BGRA_8888, 1241 WB_FORMAT_BGRX_8888, 1242 WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */ 1243}; 1244 1245struct msmfb_mdp_pp { 1246 uint32_t op; 1247 union { 1248 struct mdp_pcc_cfg_data pcc_cfg_data; 1249 struct mdp_csc_cfg_data csc_cfg_data; 1250 struct mdp_lut_cfg_data lut_cfg_data; 1251 struct mdp_qseed_cfg_data qseed_cfg_data; 1252 struct mdp_bl_scale_data bl_scale_data; 1253 struct mdp_pa_cfg_data pa_cfg_data; 1254 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 1255 struct mdp_dither_cfg_data dither_cfg_data; 1256 struct mdp_gamut_cfg_data gamut_cfg_data; 1257 struct mdp_calib_config_data calib_cfg; 1258 struct mdss_ad_init_cfg ad_init_cfg; 1259 struct mdss_calib_cfg mdss_calib_cfg; 1260 struct mdss_ad_input ad_input; 1261 struct mdp_calib_config_buffer calib_buffer; 1262 struct mdp_calib_dcm_state calib_dcm; 1263 struct mdss_ad_bl_cfg ad_bl_cfg; 1264 } data; 1265}; 1266 1267#define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 1268enum { 1269 metadata_op_none, 1270 metadata_op_base_blend, 1271 metadata_op_frame_rate, 1272 metadata_op_vic, 1273 metadata_op_wb_format, 1274 metadata_op_wb_secure, 1275 metadata_op_get_caps, 1276 metadata_op_crc, 1277 metadata_op_get_ion_fd, 1278 metadata_op_max 1279}; 1280 1281struct mdp_blend_cfg { 1282 uint32_t is_premultiplied; 1283}; 1284 1285struct mdp_mixer_cfg { 1286 uint32_t writeback_format; 1287 uint32_t alpha; 1288}; 1289 1290struct mdss_hw_caps { 1291 uint32_t mdp_rev; 1292 uint8_t rgb_pipes; 1293 uint8_t vig_pipes; 1294 uint8_t dma_pipes; 1295 uint8_t max_smp_cnt; 1296 uint8_t smp_per_pipe; 1297 uint32_t features; 1298}; 1299 1300struct msmfb_metadata { 1301 uint32_t op; 1302 uint32_t flags; 1303 union { 1304 struct mdp_misr misr_request; 1305 struct mdp_blend_cfg blend_cfg; 1306 struct mdp_mixer_cfg mixer_cfg; 1307 uint32_t panel_frame_rate; 1308 uint32_t video_info_code; 1309 struct mdss_hw_caps caps; 1310 uint8_t secure_en; 1311 int fbmem_ionfd; 1312 } data; 1313}; 1314 1315#define MDP_MAX_FENCE_FD 32 1316#define MDP_BUF_SYNC_FLAG_WAIT 1 1317#define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1318 1319struct mdp_buf_sync { 1320 uint32_t flags; 1321 uint32_t acq_fen_fd_cnt; 1322 uint32_t session_id; 1323 int *acq_fen_fd; 1324 int *rel_fen_fd; 1325 int *retire_fen_fd; 1326}; 1327 1328struct mdp_async_blit_req_list { 1329 struct mdp_buf_sync sync; 1330 uint32_t count; 1331 struct mdp_blit_req req[]; 1332}; 1333 1334#define MDP_DISPLAY_COMMIT_OVERLAY 1 1335 1336struct mdp_display_commit { 1337 uint32_t flags; 1338 uint32_t wait_for_finish; 1339 struct fb_var_screeninfo var; 1340 /* 1341 * user needs to follow guidelines as per below rules 1342 * 1. source split is enabled: l_roi = roi and r_roi = 0 1343 * 2. source split is disabled: 1344 * 2.1 split display: l_roi = l_roi and r_roi = r_roi 1345 * 2.2 non split display: l_roi = roi and r_roi = 0 1346 */ 1347 struct mdp_rect l_roi; 1348 struct mdp_rect r_roi; 1349}; 1350 1351/** 1352 * struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE 1353 * @num_overlays: Number of overlay layers as part of the frame. 1354 * @overlay_list: Pointer to a list of overlay structures identifying 1355 * the layers as part of the frame 1356 * @flags: Flags can be used to extend behavior. 1357 * @processed_overlays: Output parameter indicating how many pipes were 1358 * successful. If there are no errors this number should 1359 * match num_overlays. Otherwise it will indicate the last 1360 * successful index for overlay that couldn't be set. 1361 */ 1362struct mdp_overlay_list { 1363 uint32_t num_overlays; 1364 struct mdp_overlay **overlay_list; 1365 uint32_t flags; 1366 uint32_t processed_overlays; 1367}; 1368 1369struct mdp_page_protection { 1370 uint32_t page_protection; 1371}; 1372 1373 1374struct mdp_mixer_info { 1375 int pndx; 1376 int pnum; 1377 int ptype; 1378 int mixer_num; 1379 int z_order; 1380}; 1381 1382#define MAX_PIPE_PER_MIXER 7 1383 1384struct msmfb_mixer_info_req { 1385 int mixer_num; 1386 int cnt; 1387 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1388}; 1389 1390enum { 1391 DISPLAY_SUBSYSTEM_ID, 1392 ROTATOR_SUBSYSTEM_ID, 1393}; 1394 1395enum { 1396 MDP_IOMMU_DOMAIN_CP, 1397 MDP_IOMMU_DOMAIN_NS, 1398}; 1399 1400enum { 1401 MDP_WRITEBACK_MIRROR_OFF, 1402 MDP_WRITEBACK_MIRROR_ON, 1403 MDP_WRITEBACK_MIRROR_PAUSE, 1404 MDP_WRITEBACK_MIRROR_RESUME, 1405}; 1406 1407/* 1408 * The enum values are continued below as preprocessor macro definitions 1409 */ 1410enum mdp_color_space { 1411 MDP_CSC_ITU_R_601, 1412 MDP_CSC_ITU_R_601_FR, 1413 MDP_CSC_ITU_R_709, 1414}; 1415 1416/* 1417 * These definitions are a continuation of the mdp_color_space enum above 1418 */ 1419#define MDP_CSC_ITU_R_2020 (MDP_CSC_ITU_R_709 + 1) 1420#define MDP_CSC_ITU_R_2020_FR (MDP_CSC_ITU_R_2020 + 1) 1421 1422enum { 1423 mdp_igc_v1_7 = 1, 1424 mdp_igc_vmax, 1425 mdp_hist_lut_v1_7, 1426 mdp_hist_lut_vmax, 1427 mdp_pgc_v1_7, 1428 mdp_pgc_vmax, 1429 mdp_dither_v1_7, 1430 mdp_dither_vmax, 1431 mdp_gamut_v1_7, 1432 mdp_gamut_vmax, 1433 mdp_pa_v1_7, 1434 mdp_pa_vmax, 1435 mdp_pcc_v1_7, 1436 mdp_pcc_vmax, 1437 mdp_pp_legacy, 1438 mdp_dither_pa_v1_7, 1439 mdp_igc_v3, 1440 mdp_pp_unknown = 255 1441}; 1442 1443#define mdp_dither_pa_v1_7 mdp_dither_pa_v1_7 1444#define mdp_pp_unknown mdp_pp_unknown 1445#define mdp_igc_v3 mdp_igc_v3 1446 1447/* PP Features */ 1448enum { 1449 IGC = 1, 1450 PCC, 1451 GC, 1452 PA, 1453 GAMUT, 1454 DITHER, 1455 QSEED, 1456 HIST_LUT, 1457 HIST, 1458 PP_FEATURE_MAX, 1459 PA_DITHER, 1460 PP_MAX_FEATURES = 25, 1461}; 1462 1463#define PA_DITHER PA_DITHER 1464#define PP_MAX_FEATURES PP_MAX_FEATURES 1465 1466struct mdp_pp_feature_version { 1467 uint32_t pp_feature; 1468 uint32_t version_info; 1469}; 1470#endif /* _MSM_MDP_H_*/ 1471