1//===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the declaration of the MachineOperand class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_CODEGEN_MACHINEOPERAND_H 15#define LLVM_CODEGEN_MACHINEOPERAND_H 16 17#include "llvm/ADT/DenseMap.h" 18#include "llvm/IR/Intrinsics.h" 19#include "llvm/Support/DataTypes.h" 20#include <cassert> 21 22namespace llvm { 23 24class BlockAddress; 25class ConstantFP; 26class ConstantInt; 27class GlobalValue; 28class MachineBasicBlock; 29class MachineInstr; 30class MachineRegisterInfo; 31class MDNode; 32class ModuleSlotTracker; 33class TargetMachine; 34class TargetIntrinsicInfo; 35class TargetRegisterInfo; 36class hash_code; 37class raw_ostream; 38class MCSymbol; 39 40/// MachineOperand class - Representation of each machine instruction operand. 41/// 42/// This class isn't a POD type because it has a private constructor, but its 43/// destructor must be trivial. Functions like MachineInstr::addOperand(), 44/// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on 45/// not having to call the MachineOperand destructor. 46/// 47class MachineOperand { 48public: 49 enum MachineOperandType : unsigned char { 50 MO_Register, ///< Register operand. 51 MO_Immediate, ///< Immediate operand 52 MO_CImmediate, ///< Immediate >64bit operand 53 MO_FPImmediate, ///< Floating-point immediate operand 54 MO_MachineBasicBlock, ///< MachineBasicBlock reference 55 MO_FrameIndex, ///< Abstract Stack Frame Index 56 MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool 57 MO_TargetIndex, ///< Target-dependent index+offset operand. 58 MO_JumpTableIndex, ///< Address of indexed Jump Table for switch 59 MO_ExternalSymbol, ///< Name of external global symbol 60 MO_GlobalAddress, ///< Address of a global value 61 MO_BlockAddress, ///< Address of a basic block 62 MO_RegisterMask, ///< Mask of preserved registers. 63 MO_RegisterLiveOut, ///< Mask of live-out registers. 64 MO_Metadata, ///< Metadata reference (for debug info) 65 MO_MCSymbol, ///< MCSymbol reference (for debug/eh info) 66 MO_CFIIndex, ///< MCCFIInstruction index. 67 MO_IntrinsicID, ///< Intrinsic ID for ISel 68 MO_Predicate, ///< Generic predicate for ISel 69 MO_Last = MO_Predicate, 70 }; 71 72private: 73 /// OpKind - Specify what kind of operand this is. This discriminates the 74 /// union. 75 MachineOperandType OpKind : 8; 76 77 /// Subregister number for MO_Register. A value of 0 indicates the 78 /// MO_Register has no subReg. 79 /// 80 /// For all other kinds of operands, this field holds target-specific flags. 81 unsigned SubReg_TargetFlags : 12; 82 83 /// TiedTo - Non-zero when this register operand is tied to another register 84 /// operand. The encoding of this field is described in the block comment 85 /// before MachineInstr::tieOperands(). 86 unsigned char TiedTo : 4; 87 88 /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register 89 /// operands. 90 91 /// IsDef - True if this is a def, false if this is a use of the register. 92 /// 93 bool IsDef : 1; 94 95 /// IsImp - True if this is an implicit def or use, false if it is explicit. 96 /// 97 bool IsImp : 1; 98 99 /// IsKill - True if this instruction is the last use of the register on this 100 /// path through the function. This is only valid on uses of registers. 101 bool IsKill : 1; 102 103 /// IsDead - True if this register is never used by a subsequent instruction. 104 /// This is only valid on definitions of registers. 105 bool IsDead : 1; 106 107 /// IsUndef - True if this register operand reads an "undef" value, i.e. the 108 /// read value doesn't matter. This flag can be set on both use and def 109 /// operands. On a sub-register def operand, it refers to the part of the 110 /// register that isn't written. On a full-register def operand, it is a 111 /// noop. See readsReg(). 112 /// 113 /// This is only valid on registers. 114 /// 115 /// Note that an instruction may have multiple <undef> operands referring to 116 /// the same register. In that case, the instruction may depend on those 117 /// operands reading the same dont-care value. For example: 118 /// 119 /// %vreg1<def> = XOR %vreg2<undef>, %vreg2<undef> 120 /// 121 /// Any register can be used for %vreg2, and its value doesn't matter, but 122 /// the two operands must be the same register. 123 /// 124 bool IsUndef : 1; 125 126 /// IsInternalRead - True if this operand reads a value that was defined 127 /// inside the same instruction or bundle. This flag can be set on both use 128 /// and def operands. On a sub-register def operand, it refers to the part 129 /// of the register that isn't written. On a full-register def operand, it 130 /// is a noop. 131 /// 132 /// When this flag is set, the instruction bundle must contain at least one 133 /// other def of the register. If multiple instructions in the bundle define 134 /// the register, the meaning is target-defined. 135 bool IsInternalRead : 1; 136 137 /// IsEarlyClobber - True if this MO_Register 'def' operand is written to 138 /// by the MachineInstr before all input registers are read. This is used to 139 /// model the GCC inline asm '&' constraint modifier. 140 bool IsEarlyClobber : 1; 141 142 /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo, 143 /// not a real instruction. Such uses should be ignored during codegen. 144 bool IsDebug : 1; 145 146 /// SmallContents - This really should be part of the Contents union, but 147 /// lives out here so we can get a better packed struct. 148 /// MO_Register: Register number. 149 /// OffsetedInfo: Low bits of offset. 150 union { 151 unsigned RegNo; // For MO_Register. 152 unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi. 153 } SmallContents; 154 155 /// ParentMI - This is the instruction that this operand is embedded into. 156 /// This is valid for all operand types, when the operand is in an instr. 157 MachineInstr *ParentMI; 158 159 /// Contents union - This contains the payload for the various operand types. 160 union { 161 MachineBasicBlock *MBB; // For MO_MachineBasicBlock. 162 const ConstantFP *CFP; // For MO_FPImmediate. 163 const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit. 164 int64_t ImmVal; // For MO_Immediate. 165 const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut. 166 const MDNode *MD; // For MO_Metadata. 167 MCSymbol *Sym; // For MO_MCSymbol. 168 unsigned CFIIndex; // For MO_CFI. 169 Intrinsic::ID IntrinsicID; // For MO_IntrinsicID. 170 unsigned Pred; // For MO_Predicate 171 172 struct { // For MO_Register. 173 // Register number is in SmallContents.RegNo. 174 MachineOperand *Prev; // Access list for register. See MRI. 175 MachineOperand *Next; 176 } Reg; 177 178 /// OffsetedInfo - This struct contains the offset and an object identifier. 179 /// this represent the object as with an optional offset from it. 180 struct { 181 union { 182 int Index; // For MO_*Index - The index itself. 183 const char *SymbolName; // For MO_ExternalSymbol. 184 const GlobalValue *GV; // For MO_GlobalAddress. 185 const BlockAddress *BA; // For MO_BlockAddress. 186 } Val; 187 // Low bits of offset are in SmallContents.OffsetLo. 188 int OffsetHi; // An offset from the object, high 32 bits. 189 } OffsetedInfo; 190 } Contents; 191 192 explicit MachineOperand(MachineOperandType K) 193 : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {} 194public: 195 /// getType - Returns the MachineOperandType for this operand. 196 /// 197 MachineOperandType getType() const { return (MachineOperandType)OpKind; } 198 199 unsigned getTargetFlags() const { 200 return isReg() ? 0 : SubReg_TargetFlags; 201 } 202 void setTargetFlags(unsigned F) { 203 assert(!isReg() && "Register operands can't have target flags"); 204 SubReg_TargetFlags = F; 205 assert(SubReg_TargetFlags == F && "Target flags out of range"); 206 } 207 void addTargetFlag(unsigned F) { 208 assert(!isReg() && "Register operands can't have target flags"); 209 SubReg_TargetFlags |= F; 210 assert((SubReg_TargetFlags & F) && "Target flags out of range"); 211 } 212 213 214 /// getParent - Return the instruction that this operand belongs to. 215 /// 216 MachineInstr *getParent() { return ParentMI; } 217 const MachineInstr *getParent() const { return ParentMI; } 218 219 /// clearParent - Reset the parent pointer. 220 /// 221 /// The MachineOperand copy constructor also copies ParentMI, expecting the 222 /// original to be deleted. If a MachineOperand is ever stored outside a 223 /// MachineInstr, the parent pointer must be cleared. 224 /// 225 /// Never call clearParent() on an operand in a MachineInstr. 226 /// 227 void clearParent() { ParentMI = nullptr; } 228 229 void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr, 230 const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const; 231 void print(raw_ostream &os, ModuleSlotTracker &MST, 232 const TargetRegisterInfo *TRI = nullptr, 233 const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const; 234 void dump() const; 235 236 //===--------------------------------------------------------------------===// 237 // Accessors that tell you what kind of MachineOperand you're looking at. 238 //===--------------------------------------------------------------------===// 239 240 /// isReg - Tests if this is a MO_Register operand. 241 bool isReg() const { return OpKind == MO_Register; } 242 /// isImm - Tests if this is a MO_Immediate operand. 243 bool isImm() const { return OpKind == MO_Immediate; } 244 /// isCImm - Test if this is a MO_CImmediate operand. 245 bool isCImm() const { return OpKind == MO_CImmediate; } 246 /// isFPImm - Tests if this is a MO_FPImmediate operand. 247 bool isFPImm() const { return OpKind == MO_FPImmediate; } 248 /// isMBB - Tests if this is a MO_MachineBasicBlock operand. 249 bool isMBB() const { return OpKind == MO_MachineBasicBlock; } 250 /// isFI - Tests if this is a MO_FrameIndex operand. 251 bool isFI() const { return OpKind == MO_FrameIndex; } 252 /// isCPI - Tests if this is a MO_ConstantPoolIndex operand. 253 bool isCPI() const { return OpKind == MO_ConstantPoolIndex; } 254 /// isTargetIndex - Tests if this is a MO_TargetIndex operand. 255 bool isTargetIndex() const { return OpKind == MO_TargetIndex; } 256 /// isJTI - Tests if this is a MO_JumpTableIndex operand. 257 bool isJTI() const { return OpKind == MO_JumpTableIndex; } 258 /// isGlobal - Tests if this is a MO_GlobalAddress operand. 259 bool isGlobal() const { return OpKind == MO_GlobalAddress; } 260 /// isSymbol - Tests if this is a MO_ExternalSymbol operand. 261 bool isSymbol() const { return OpKind == MO_ExternalSymbol; } 262 /// isBlockAddress - Tests if this is a MO_BlockAddress operand. 263 bool isBlockAddress() const { return OpKind == MO_BlockAddress; } 264 /// isRegMask - Tests if this is a MO_RegisterMask operand. 265 bool isRegMask() const { return OpKind == MO_RegisterMask; } 266 /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand. 267 bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; } 268 /// isMetadata - Tests if this is a MO_Metadata operand. 269 bool isMetadata() const { return OpKind == MO_Metadata; } 270 bool isMCSymbol() const { return OpKind == MO_MCSymbol; } 271 bool isCFIIndex() const { return OpKind == MO_CFIIndex; } 272 bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; } 273 bool isPredicate() const { return OpKind == MO_Predicate; } 274 //===--------------------------------------------------------------------===// 275 // Accessors for Register Operands 276 //===--------------------------------------------------------------------===// 277 278 /// getReg - Returns the register number. 279 unsigned getReg() const { 280 assert(isReg() && "This is not a register operand!"); 281 return SmallContents.RegNo; 282 } 283 284 unsigned getSubReg() const { 285 assert(isReg() && "Wrong MachineOperand accessor"); 286 return SubReg_TargetFlags; 287 } 288 289 bool isUse() const { 290 assert(isReg() && "Wrong MachineOperand accessor"); 291 return !IsDef; 292 } 293 294 bool isDef() const { 295 assert(isReg() && "Wrong MachineOperand accessor"); 296 return IsDef; 297 } 298 299 bool isImplicit() const { 300 assert(isReg() && "Wrong MachineOperand accessor"); 301 return IsImp; 302 } 303 304 bool isDead() const { 305 assert(isReg() && "Wrong MachineOperand accessor"); 306 return IsDead; 307 } 308 309 bool isKill() const { 310 assert(isReg() && "Wrong MachineOperand accessor"); 311 return IsKill; 312 } 313 314 bool isUndef() const { 315 assert(isReg() && "Wrong MachineOperand accessor"); 316 return IsUndef; 317 } 318 319 bool isInternalRead() const { 320 assert(isReg() && "Wrong MachineOperand accessor"); 321 return IsInternalRead; 322 } 323 324 bool isEarlyClobber() const { 325 assert(isReg() && "Wrong MachineOperand accessor"); 326 return IsEarlyClobber; 327 } 328 329 bool isTied() const { 330 assert(isReg() && "Wrong MachineOperand accessor"); 331 return TiedTo; 332 } 333 334 bool isDebug() const { 335 assert(isReg() && "Wrong MachineOperand accessor"); 336 return IsDebug; 337 } 338 339 /// readsReg - Returns true if this operand reads the previous value of its 340 /// register. A use operand with the <undef> flag set doesn't read its 341 /// register. A sub-register def implicitly reads the other parts of the 342 /// register being redefined unless the <undef> flag is set. 343 /// 344 /// This refers to reading the register value from before the current 345 /// instruction or bundle. Internal bundle reads are not included. 346 bool readsReg() const { 347 assert(isReg() && "Wrong MachineOperand accessor"); 348 return !isUndef() && !isInternalRead() && (isUse() || getSubReg()); 349 } 350 351 //===--------------------------------------------------------------------===// 352 // Mutators for Register Operands 353 //===--------------------------------------------------------------------===// 354 355 /// Change the register this operand corresponds to. 356 /// 357 void setReg(unsigned Reg); 358 359 void setSubReg(unsigned subReg) { 360 assert(isReg() && "Wrong MachineOperand mutator"); 361 SubReg_TargetFlags = subReg; 362 assert(SubReg_TargetFlags == subReg && "SubReg out of range"); 363 } 364 365 /// substVirtReg - Substitute the current register with the virtual 366 /// subregister Reg:SubReg. Take any existing SubReg index into account, 367 /// using TargetRegisterInfo to compose the subreg indices if necessary. 368 /// Reg must be a virtual register, SubIdx can be 0. 369 /// 370 void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&); 371 372 /// substPhysReg - Substitute the current register with the physical register 373 /// Reg, taking any existing SubReg into account. For instance, 374 /// substPhysReg(%EAX) will change %reg1024:sub_8bit to %AL. 375 /// 376 void substPhysReg(unsigned Reg, const TargetRegisterInfo&); 377 378 void setIsUse(bool Val = true) { setIsDef(!Val); } 379 380 void setIsDef(bool Val = true); 381 382 void setImplicit(bool Val = true) { 383 assert(isReg() && "Wrong MachineOperand mutator"); 384 IsImp = Val; 385 } 386 387 void setIsKill(bool Val = true) { 388 assert(isReg() && !IsDef && "Wrong MachineOperand mutator"); 389 assert((!Val || !isDebug()) && "Marking a debug operation as kill"); 390 IsKill = Val; 391 } 392 393 void setIsDead(bool Val = true) { 394 assert(isReg() && IsDef && "Wrong MachineOperand mutator"); 395 IsDead = Val; 396 } 397 398 void setIsUndef(bool Val = true) { 399 assert(isReg() && "Wrong MachineOperand mutator"); 400 IsUndef = Val; 401 } 402 403 void setIsInternalRead(bool Val = true) { 404 assert(isReg() && "Wrong MachineOperand mutator"); 405 IsInternalRead = Val; 406 } 407 408 void setIsEarlyClobber(bool Val = true) { 409 assert(isReg() && IsDef && "Wrong MachineOperand mutator"); 410 IsEarlyClobber = Val; 411 } 412 413 void setIsDebug(bool Val = true) { 414 assert(isReg() && !IsDef && "Wrong MachineOperand mutator"); 415 IsDebug = Val; 416 } 417 418 //===--------------------------------------------------------------------===// 419 // Accessors for various operand types. 420 //===--------------------------------------------------------------------===// 421 422 int64_t getImm() const { 423 assert(isImm() && "Wrong MachineOperand accessor"); 424 return Contents.ImmVal; 425 } 426 427 const ConstantInt *getCImm() const { 428 assert(isCImm() && "Wrong MachineOperand accessor"); 429 return Contents.CI; 430 } 431 432 const ConstantFP *getFPImm() const { 433 assert(isFPImm() && "Wrong MachineOperand accessor"); 434 return Contents.CFP; 435 } 436 437 MachineBasicBlock *getMBB() const { 438 assert(isMBB() && "Wrong MachineOperand accessor"); 439 return Contents.MBB; 440 } 441 442 int getIndex() const { 443 assert((isFI() || isCPI() || isTargetIndex() || isJTI()) && 444 "Wrong MachineOperand accessor"); 445 return Contents.OffsetedInfo.Val.Index; 446 } 447 448 const GlobalValue *getGlobal() const { 449 assert(isGlobal() && "Wrong MachineOperand accessor"); 450 return Contents.OffsetedInfo.Val.GV; 451 } 452 453 const BlockAddress *getBlockAddress() const { 454 assert(isBlockAddress() && "Wrong MachineOperand accessor"); 455 return Contents.OffsetedInfo.Val.BA; 456 } 457 458 MCSymbol *getMCSymbol() const { 459 assert(isMCSymbol() && "Wrong MachineOperand accessor"); 460 return Contents.Sym; 461 } 462 463 unsigned getCFIIndex() const { 464 assert(isCFIIndex() && "Wrong MachineOperand accessor"); 465 return Contents.CFIIndex; 466 } 467 468 Intrinsic::ID getIntrinsicID() const { 469 assert(isIntrinsicID() && "Wrong MachineOperand accessor"); 470 return Contents.IntrinsicID; 471 } 472 473 unsigned getPredicate() const { 474 assert(isPredicate() && "Wrong MachineOperand accessor"); 475 return Contents.Pred; 476 } 477 478 /// Return the offset from the symbol in this operand. This always returns 0 479 /// for ExternalSymbol operands. 480 int64_t getOffset() const { 481 assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() || 482 isTargetIndex() || isBlockAddress()) && 483 "Wrong MachineOperand accessor"); 484 return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) | 485 SmallContents.OffsetLo; 486 } 487 488 const char *getSymbolName() const { 489 assert(isSymbol() && "Wrong MachineOperand accessor"); 490 return Contents.OffsetedInfo.Val.SymbolName; 491 } 492 493 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg. 494 /// It is sometimes necessary to detach the register mask pointer from its 495 /// machine operand. This static method can be used for such detached bit 496 /// mask pointers. 497 static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) { 498 // See TargetRegisterInfo.h. 499 assert(PhysReg < (1u << 30) && "Not a physical register"); 500 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32)); 501 } 502 503 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg. 504 bool clobbersPhysReg(unsigned PhysReg) const { 505 return clobbersPhysReg(getRegMask(), PhysReg); 506 } 507 508 /// getRegMask - Returns a bit mask of registers preserved by this RegMask 509 /// operand. 510 const uint32_t *getRegMask() const { 511 assert(isRegMask() && "Wrong MachineOperand accessor"); 512 return Contents.RegMask; 513 } 514 515 /// getRegLiveOut - Returns a bit mask of live-out registers. 516 const uint32_t *getRegLiveOut() const { 517 assert(isRegLiveOut() && "Wrong MachineOperand accessor"); 518 return Contents.RegMask; 519 } 520 521 const MDNode *getMetadata() const { 522 assert(isMetadata() && "Wrong MachineOperand accessor"); 523 return Contents.MD; 524 } 525 526 //===--------------------------------------------------------------------===// 527 // Mutators for various operand types. 528 //===--------------------------------------------------------------------===// 529 530 void setImm(int64_t immVal) { 531 assert(isImm() && "Wrong MachineOperand mutator"); 532 Contents.ImmVal = immVal; 533 } 534 535 void setFPImm(const ConstantFP *CFP) { 536 assert(isFPImm() && "Wrong MachineOperand mutator"); 537 Contents.CFP = CFP; 538 } 539 540 void setOffset(int64_t Offset) { 541 assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() || 542 isTargetIndex() || isBlockAddress()) && 543 "Wrong MachineOperand mutator"); 544 SmallContents.OffsetLo = unsigned(Offset); 545 Contents.OffsetedInfo.OffsetHi = int(Offset >> 32); 546 } 547 548 void setIndex(int Idx) { 549 assert((isFI() || isCPI() || isTargetIndex() || isJTI()) && 550 "Wrong MachineOperand mutator"); 551 Contents.OffsetedInfo.Val.Index = Idx; 552 } 553 554 void setMetadata(const MDNode *MD) { 555 assert(isMetadata() && "Wrong MachineOperand mutator"); 556 Contents.MD = MD; 557 } 558 559 void setMBB(MachineBasicBlock *MBB) { 560 assert(isMBB() && "Wrong MachineOperand mutator"); 561 Contents.MBB = MBB; 562 } 563 564 /// Sets value of register mask operand referencing Mask. The 565 /// operand does not take ownership of the memory referenced by Mask, it must 566 /// remain valid for the lifetime of the operand. See CreateRegMask(). 567 /// Any physreg with a 0 bit in the mask is clobbered by the instruction. 568 void setRegMask(const uint32_t *RegMaskPtr) { 569 assert(isRegMask() && "Wrong MachineOperand mutator"); 570 Contents.RegMask = RegMaskPtr; 571 } 572 573 //===--------------------------------------------------------------------===// 574 // Other methods. 575 //===--------------------------------------------------------------------===// 576 577 /// Returns true if this operand is identical to the specified operand except 578 /// for liveness related flags (isKill, isUndef and isDead). 579 bool isIdenticalTo(const MachineOperand &Other) const; 580 581 /// \brief MachineOperand hash_value overload. 582 /// 583 /// Note that this includes the same information in the hash that 584 /// isIdenticalTo uses for comparison. It is thus suited for use in hash 585 /// tables which use that function for equality comparisons only. 586 friend hash_code hash_value(const MachineOperand &MO); 587 588 /// ChangeToImmediate - Replace this operand with a new immediate operand of 589 /// the specified value. If an operand is known to be an immediate already, 590 /// the setImm method should be used. 591 void ChangeToImmediate(int64_t ImmVal); 592 593 /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand 594 /// of the specified value. If an operand is known to be an FP immediate 595 /// already, the setFPImm method should be used. 596 void ChangeToFPImmediate(const ConstantFP *FPImm); 597 598 /// ChangeToES - Replace this operand with a new external symbol operand. 599 void ChangeToES(const char *SymName, unsigned char TargetFlags = 0); 600 601 /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand. 602 void ChangeToMCSymbol(MCSymbol *Sym); 603 604 /// Replace this operand with a frame index. 605 void ChangeToFrameIndex(int Idx); 606 607 /// Replace this operand with a target index. 608 void ChangeToTargetIndex(unsigned Idx, int64_t Offset, 609 unsigned char TargetFlags = 0); 610 611 /// ChangeToRegister - Replace this operand with a new register operand of 612 /// the specified value. If an operand is known to be an register already, 613 /// the setReg method should be used. 614 void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false, 615 bool isKill = false, bool isDead = false, 616 bool isUndef = false, bool isDebug = false); 617 618 //===--------------------------------------------------------------------===// 619 // Construction methods. 620 //===--------------------------------------------------------------------===// 621 622 static MachineOperand CreateImm(int64_t Val) { 623 MachineOperand Op(MachineOperand::MO_Immediate); 624 Op.setImm(Val); 625 return Op; 626 } 627 628 static MachineOperand CreateCImm(const ConstantInt *CI) { 629 MachineOperand Op(MachineOperand::MO_CImmediate); 630 Op.Contents.CI = CI; 631 return Op; 632 } 633 634 static MachineOperand CreateFPImm(const ConstantFP *CFP) { 635 MachineOperand Op(MachineOperand::MO_FPImmediate); 636 Op.Contents.CFP = CFP; 637 return Op; 638 } 639 640 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false, 641 bool isKill = false, bool isDead = false, 642 bool isUndef = false, 643 bool isEarlyClobber = false, 644 unsigned SubReg = 0, 645 bool isDebug = false, 646 bool isInternalRead = false) { 647 assert(!(isDead && !isDef) && "Dead flag on non-def"); 648 assert(!(isKill && isDef) && "Kill flag on def"); 649 MachineOperand Op(MachineOperand::MO_Register); 650 Op.IsDef = isDef; 651 Op.IsImp = isImp; 652 Op.IsKill = isKill; 653 Op.IsDead = isDead; 654 Op.IsUndef = isUndef; 655 Op.IsInternalRead = isInternalRead; 656 Op.IsEarlyClobber = isEarlyClobber; 657 Op.TiedTo = 0; 658 Op.IsDebug = isDebug; 659 Op.SmallContents.RegNo = Reg; 660 Op.Contents.Reg.Prev = nullptr; 661 Op.Contents.Reg.Next = nullptr; 662 Op.setSubReg(SubReg); 663 return Op; 664 } 665 static MachineOperand CreateMBB(MachineBasicBlock *MBB, 666 unsigned char TargetFlags = 0) { 667 MachineOperand Op(MachineOperand::MO_MachineBasicBlock); 668 Op.setMBB(MBB); 669 Op.setTargetFlags(TargetFlags); 670 return Op; 671 } 672 static MachineOperand CreateFI(int Idx) { 673 MachineOperand Op(MachineOperand::MO_FrameIndex); 674 Op.setIndex(Idx); 675 return Op; 676 } 677 static MachineOperand CreateCPI(unsigned Idx, int Offset, 678 unsigned char TargetFlags = 0) { 679 MachineOperand Op(MachineOperand::MO_ConstantPoolIndex); 680 Op.setIndex(Idx); 681 Op.setOffset(Offset); 682 Op.setTargetFlags(TargetFlags); 683 return Op; 684 } 685 static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, 686 unsigned char TargetFlags = 0) { 687 MachineOperand Op(MachineOperand::MO_TargetIndex); 688 Op.setIndex(Idx); 689 Op.setOffset(Offset); 690 Op.setTargetFlags(TargetFlags); 691 return Op; 692 } 693 static MachineOperand CreateJTI(unsigned Idx, 694 unsigned char TargetFlags = 0) { 695 MachineOperand Op(MachineOperand::MO_JumpTableIndex); 696 Op.setIndex(Idx); 697 Op.setTargetFlags(TargetFlags); 698 return Op; 699 } 700 static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, 701 unsigned char TargetFlags = 0) { 702 MachineOperand Op(MachineOperand::MO_GlobalAddress); 703 Op.Contents.OffsetedInfo.Val.GV = GV; 704 Op.setOffset(Offset); 705 Op.setTargetFlags(TargetFlags); 706 return Op; 707 } 708 static MachineOperand CreateES(const char *SymName, 709 unsigned char TargetFlags = 0) { 710 MachineOperand Op(MachineOperand::MO_ExternalSymbol); 711 Op.Contents.OffsetedInfo.Val.SymbolName = SymName; 712 Op.setOffset(0); // Offset is always 0. 713 Op.setTargetFlags(TargetFlags); 714 return Op; 715 } 716 static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, 717 unsigned char TargetFlags = 0) { 718 MachineOperand Op(MachineOperand::MO_BlockAddress); 719 Op.Contents.OffsetedInfo.Val.BA = BA; 720 Op.setOffset(Offset); 721 Op.setTargetFlags(TargetFlags); 722 return Op; 723 } 724 /// CreateRegMask - Creates a register mask operand referencing Mask. The 725 /// operand does not take ownership of the memory referenced by Mask, it must 726 /// remain valid for the lifetime of the operand. 727 /// 728 /// A RegMask operand represents a set of non-clobbered physical registers on 729 /// an instruction that clobbers many registers, typically a call. The bit 730 /// mask has a bit set for each physreg that is preserved by this 731 /// instruction, as described in the documentation for 732 /// TargetRegisterInfo::getCallPreservedMask(). 733 /// 734 /// Any physreg with a 0 bit in the mask is clobbered by the instruction. 735 /// 736 static MachineOperand CreateRegMask(const uint32_t *Mask) { 737 assert(Mask && "Missing register mask"); 738 MachineOperand Op(MachineOperand::MO_RegisterMask); 739 Op.Contents.RegMask = Mask; 740 return Op; 741 } 742 static MachineOperand CreateRegLiveOut(const uint32_t *Mask) { 743 assert(Mask && "Missing live-out register mask"); 744 MachineOperand Op(MachineOperand::MO_RegisterLiveOut); 745 Op.Contents.RegMask = Mask; 746 return Op; 747 } 748 static MachineOperand CreateMetadata(const MDNode *Meta) { 749 MachineOperand Op(MachineOperand::MO_Metadata); 750 Op.Contents.MD = Meta; 751 return Op; 752 } 753 754 static MachineOperand CreateMCSymbol(MCSymbol *Sym, 755 unsigned char TargetFlags = 0) { 756 MachineOperand Op(MachineOperand::MO_MCSymbol); 757 Op.Contents.Sym = Sym; 758 Op.setOffset(0); 759 Op.setTargetFlags(TargetFlags); 760 return Op; 761 } 762 763 static MachineOperand CreateCFIIndex(unsigned CFIIndex) { 764 MachineOperand Op(MachineOperand::MO_CFIIndex); 765 Op.Contents.CFIIndex = CFIIndex; 766 return Op; 767 } 768 769 static MachineOperand CreateIntrinsicID(Intrinsic::ID ID) { 770 MachineOperand Op(MachineOperand::MO_IntrinsicID); 771 Op.Contents.IntrinsicID = ID; 772 return Op; 773 } 774 775 static MachineOperand CreatePredicate(unsigned Pred) { 776 MachineOperand Op(MachineOperand::MO_Predicate); 777 Op.Contents.Pred = Pred; 778 return Op; 779 } 780 781 friend class MachineInstr; 782 friend class MachineRegisterInfo; 783private: 784 void removeRegFromUses(); 785 786 /// Artificial kinds for DenseMap usage. 787 enum : unsigned char { 788 MO_Empty = MO_Last + 1, 789 MO_Tombstone, 790 }; 791 792 friend struct DenseMapInfo<MachineOperand>; 793 794 //===--------------------------------------------------------------------===// 795 // Methods for handling register use/def lists. 796 //===--------------------------------------------------------------------===// 797 798 /// isOnRegUseList - Return true if this operand is on a register use/def list 799 /// or false if not. This can only be called for register operands that are 800 /// part of a machine instruction. 801 bool isOnRegUseList() const { 802 assert(isReg() && "Can only add reg operand to use lists"); 803 return Contents.Reg.Prev != nullptr; 804 } 805}; 806 807template <> struct DenseMapInfo<MachineOperand> { 808 static MachineOperand getEmptyKey() { 809 return MachineOperand(static_cast<MachineOperand::MachineOperandType>( 810 MachineOperand::MO_Empty)); 811 } 812 static MachineOperand getTombstoneKey() { 813 return MachineOperand(static_cast<MachineOperand::MachineOperandType>( 814 MachineOperand::MO_Tombstone)); 815 } 816 static unsigned getHashValue(const MachineOperand &MO) { 817 return hash_value(MO); 818 } 819 static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS) { 820 if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>( 821 MachineOperand::MO_Empty) || 822 LHS.getType() == static_cast<MachineOperand::MachineOperandType>( 823 MachineOperand::MO_Tombstone)) 824 return LHS.getType() == RHS.getType(); 825 return LHS.isIdenticalTo(RHS); 826 } 827}; 828 829inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand& MO) { 830 MO.print(OS, nullptr); 831 return OS; 832} 833 834 // See friend declaration above. This additional declaration is required in 835 // order to compile LLVM with IBM xlC compiler. 836 hash_code hash_value(const MachineOperand &MO); 837} // End llvm namespace 838 839#endif 840