1//===- llvm/MC/MCSubtargetInfo.h - Subtarget Information --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subtarget options of a Target machine. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_MC_MCSUBTARGETINFO_H 15#define LLVM_MC_MCSUBTARGETINFO_H 16 17#include "llvm/ADT/ArrayRef.h" 18#include "llvm/ADT/StringRef.h" 19#include "llvm/ADT/Triple.h" 20#include "llvm/MC/MCInstrItineraries.h" 21#include "llvm/MC/MCSchedule.h" 22#include "llvm/MC/SubtargetFeature.h" 23#include <algorithm> 24#include <cassert> 25#include <cstdint> 26#include <string> 27 28namespace llvm { 29 30class MachineInstr; 31class MCInst; 32 33//===----------------------------------------------------------------------===// 34/// 35/// MCSubtargetInfo - Generic base class for all target subtargets. 36/// 37class MCSubtargetInfo { 38 Triple TargetTriple; // Target triple 39 std::string CPU; // CPU being targeted. 40 ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list 41 ArrayRef<SubtargetFeatureKV> ProcDesc; // Processor descriptions 42 43 // Scheduler machine model 44 const SubtargetInfoKV *ProcSchedModels; 45 const MCWriteProcResEntry *WriteProcResTable; 46 const MCWriteLatencyEntry *WriteLatencyTable; 47 const MCReadAdvanceEntry *ReadAdvanceTable; 48 const MCSchedModel *CPUSchedModel; 49 50 const InstrStage *Stages; // Instruction itinerary stages 51 const unsigned *OperandCycles; // Itinerary operand cycles 52 const unsigned *ForwardingPaths; // Forwarding paths 53 FeatureBitset FeatureBits; // Feature bits for current CPU + FS 54 55public: 56 MCSubtargetInfo(const MCSubtargetInfo &) = default; 57 MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS, 58 ArrayRef<SubtargetFeatureKV> PF, 59 ArrayRef<SubtargetFeatureKV> PD, 60 const SubtargetInfoKV *ProcSched, 61 const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, 62 const MCReadAdvanceEntry *RA, const InstrStage *IS, 63 const unsigned *OC, const unsigned *FP); 64 MCSubtargetInfo() = delete; 65 MCSubtargetInfo &operator=(const MCSubtargetInfo &) = delete; 66 MCSubtargetInfo &operator=(MCSubtargetInfo &&) = delete; 67 virtual ~MCSubtargetInfo() = default; 68 69 /// getTargetTriple - Return the target triple string. 70 const Triple &getTargetTriple() const { return TargetTriple; } 71 72 /// getCPU - Return the CPU string. 73 StringRef getCPU() const { 74 return CPU; 75 } 76 77 /// getFeatureBits - Return the feature bits. 78 /// 79 const FeatureBitset& getFeatureBits() const { 80 return FeatureBits; 81 } 82 83 /// setFeatureBits - Set the feature bits. 84 /// 85 void setFeatureBits(const FeatureBitset &FeatureBits_) { 86 FeatureBits = FeatureBits_; 87 } 88 89 bool hasFeature(unsigned Feature) const { 90 return FeatureBits[Feature]; 91 } 92 93protected: 94 /// Initialize the scheduling model and feature bits. 95 /// 96 /// FIXME: Find a way to stick this in the constructor, since it should only 97 /// be called during initialization. 98 void InitMCProcessorInfo(StringRef CPU, StringRef FS); 99 100public: 101 /// Set the features to the default for the given CPU with an appended feature 102 /// string. 103 void setDefaultFeatures(StringRef CPU, StringRef FS); 104 105 /// ToggleFeature - Toggle a feature and returns the re-computed feature 106 /// bits. This version does not change the implied bits. 107 FeatureBitset ToggleFeature(uint64_t FB); 108 109 /// ToggleFeature - Toggle a feature and returns the re-computed feature 110 /// bits. This version does not change the implied bits. 111 FeatureBitset ToggleFeature(const FeatureBitset& FB); 112 113 /// ToggleFeature - Toggle a set of features and returns the re-computed 114 /// feature bits. This version will also change all implied bits. 115 FeatureBitset ToggleFeature(StringRef FS); 116 117 /// Apply a feature flag and return the re-computed feature bits, including 118 /// all feature bits implied by the flag. 119 FeatureBitset ApplyFeatureFlag(StringRef FS); 120 121 /// Check whether the subtarget features are enabled/disabled as per 122 /// the provided string, ignoring all other features. 123 bool checkFeatures(StringRef FS) const; 124 125 /// getSchedModelForCPU - Get the machine model of a CPU. 126 /// 127 const MCSchedModel &getSchedModelForCPU(StringRef CPU) const; 128 129 /// Get the machine model for this subtarget's CPU. 130 const MCSchedModel &getSchedModel() const { return *CPUSchedModel; } 131 132 /// Return an iterator at the first process resource consumed by the given 133 /// scheduling class. 134 const MCWriteProcResEntry *getWriteProcResBegin( 135 const MCSchedClassDesc *SC) const { 136 return &WriteProcResTable[SC->WriteProcResIdx]; 137 } 138 const MCWriteProcResEntry *getWriteProcResEnd( 139 const MCSchedClassDesc *SC) const { 140 return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries; 141 } 142 143 const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC, 144 unsigned DefIdx) const { 145 assert(DefIdx < SC->NumWriteLatencyEntries && 146 "MachineModel does not specify a WriteResource for DefIdx"); 147 148 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx]; 149 } 150 151 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, 152 unsigned WriteResID) const { 153 // TODO: The number of read advance entries in a class can be significant 154 // (~50). Consider compressing the WriteID into a dense ID of those that are 155 // used by ReadAdvance and representing them as a bitset. 156 for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx], 157 *E = I + SC->NumReadAdvanceEntries; I != E; ++I) { 158 if (I->UseIdx < UseIdx) 159 continue; 160 if (I->UseIdx > UseIdx) 161 break; 162 // Find the first WriteResIdx match, which has the highest cycle count. 163 if (!I->WriteResourceID || I->WriteResourceID == WriteResID) { 164 return I->Cycles; 165 } 166 } 167 return 0; 168 } 169 170 /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU. 171 /// 172 InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const; 173 174 /// Initialize an InstrItineraryData instance. 175 void initInstrItins(InstrItineraryData &InstrItins) const; 176 177 /// Check whether the CPU string is valid. 178 bool isCPUStringValid(StringRef CPU) const { 179 auto Found = std::lower_bound(ProcDesc.begin(), ProcDesc.end(), CPU); 180 return Found != ProcDesc.end() && StringRef(Found->Key) == CPU; 181 } 182 183 /// Returns string representation of scheduler comment 184 virtual std::string getSchedInfoStr(const MachineInstr &MI) const { 185 return {}; 186 } 187 188 virtual std::string getSchedInfoStr(MCInst const &MCI) const { 189 return {}; 190 } 191}; 192 193} // end namespace llvm 194 195#endif // LLVM_MC_MCSUBTARGETINFO_H 196