dbri.c revision 470f1f1a1c2597fab98339ab0966dbf602d604f0
1/* 2 * Driver for DBRI sound chip found on Sparcs. 3 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net) 4 * 5 * Based entirely upon drivers/sbus/audio/dbri.c which is: 6 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de) 7 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org) 8 * 9 * This is the lowlevel driver for the DBRI & MMCODEC duo used for ISDN & AUDIO 10 * on Sun SPARCstation 10, 20, LX and Voyager models. 11 * 12 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel 13 * data time multiplexer with ISDN support (aka T7259) 14 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel. 15 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?). 16 * Documentation: 17 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Tranceiver" from 18 * Sparc Technology Business (courtesy of Sun Support) 19 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent 20 * available from the Lucent (formarly AT&T microelectronics) home 21 * page. 22 * - http://www.freesoft.org/Linux/DBRI/ 23 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec 24 * Interfaces: CHI, Audio In & Out, 2 bits parallel 25 * Documentation: from the Crystal Semiconductor home page. 26 * 27 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between 28 * memory and a serial device (long pipes, nr 0-15) or between two serial 29 * devices (short pipes, nr 16-31), or simply send a fixed data to a serial 30 * device (short pipes). 31 * A timeslot defines the bit-offset and nr of bits read from a serial device. 32 * The timeslots are linked to 6 circular lists, one for each direction for 33 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes 34 * (the second one is a monitor/tee pipe, valid only for serial input). 35 * 36 * The mmcodec is connected via the CHI bus and needs the data & some 37 * parameters (volume, output selection) timemultiplexed in 8 byte 38 * chunks. It also has a control mode, which serves for audio format setting. 39 * 40 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on 41 * the same CHI bus, so I thought perhaps it is possible to use the onboard 42 * & the speakerbox codec simultanously, giving 2 (not very independent :-) 43 * audio devices. But the SUN HW group decided against it, at least on my 44 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly 45 * connected. 46 * 47 * I've tried to stick to the following function naming conventions: 48 * snd_* ALSA stuff 49 * cs4215_* CS4215 codec specific stuff 50 * dbri_* DBRI high-level stuff 51 * other DBRI low-level stuff 52 */ 53 54#include <sound/driver.h> 55#include <linux/interrupt.h> 56#include <linux/delay.h> 57 58#include <sound/core.h> 59#include <sound/pcm.h> 60#include <sound/pcm_params.h> 61#include <sound/info.h> 62#include <sound/control.h> 63#include <sound/initval.h> 64 65#include <asm/irq.h> 66#include <asm/io.h> 67#include <asm/sbus.h> 68#include <asm/atomic.h> 69 70MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets"); 71MODULE_DESCRIPTION("Sun DBRI"); 72MODULE_LICENSE("GPL"); 73MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}"); 74 75static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 76static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 77static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 78 79module_param_array(index, int, NULL, 0444); 80MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard."); 81module_param_array(id, charp, NULL, 0444); 82MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard."); 83module_param_array(enable, bool, NULL, 0444); 84MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard."); 85 86#define DBRI_DEBUG 87 88#define D_INT (1<<0) 89#define D_GEN (1<<1) 90#define D_CMD (1<<2) 91#define D_MM (1<<3) 92#define D_USR (1<<4) 93#define D_DESC (1<<5) 94 95static int dbri_debug; 96module_param(dbri_debug, int, 0644); 97MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard."); 98 99#ifdef DBRI_DEBUG 100static char *cmds[] = { 101 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS", 102 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV" 103}; 104 105#define dprintk(a, x...) if(dbri_debug & a) printk(KERN_DEBUG x) 106 107#else 108#define dprintk(a, x...) 109 110#endif /* DBRI_DEBUG */ 111 112#define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \ 113 (intr << 27) | \ 114 value) 115 116/*************************************************************************** 117 CS4215 specific definitions and structures 118****************************************************************************/ 119 120struct cs4215 { 121 __u8 data[4]; /* Data mode: Time slots 5-8 */ 122 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */ 123 __u8 onboard; 124 __u8 offset; /* Bit offset from frame sync to time slot 1 */ 125 volatile __u32 status; 126 volatile __u32 version; 127 __u8 precision; /* In bits, either 8 or 16 */ 128 __u8 channels; /* 1 or 2 */ 129}; 130 131/* 132 * Control mode first 133 */ 134 135/* Time Slot 1, Status register */ 136#define CS4215_CLB (1<<2) /* Control Latch Bit */ 137#define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */ 138 /* 0: line: 2.8V, speaker 8V */ 139#define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */ 140#define CS4215_RSRVD_1 (1<<5) 141 142/* Time Slot 2, Data Format Register */ 143#define CS4215_DFR_LINEAR16 0 144#define CS4215_DFR_ULAW 1 145#define CS4215_DFR_ALAW 2 146#define CS4215_DFR_LINEAR8 3 147#define CS4215_DFR_STEREO (1<<2) 148static struct { 149 unsigned short freq; 150 unsigned char xtal; 151 unsigned char csval; 152} CS4215_FREQ[] = { 153 { 8000, (1 << 4), (0 << 3) }, 154 { 16000, (1 << 4), (1 << 3) }, 155 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */ 156 { 32000, (1 << 4), (3 << 3) }, 157 /* { NA, (1 << 4), (4 << 3) }, */ 158 /* { NA, (1 << 4), (5 << 3) }, */ 159 { 48000, (1 << 4), (6 << 3) }, 160 { 9600, (1 << 4), (7 << 3) }, 161 { 5513, (2 << 4), (0 << 3) }, /* Actually 5512.5 */ 162 { 11025, (2 << 4), (1 << 3) }, 163 { 18900, (2 << 4), (2 << 3) }, 164 { 22050, (2 << 4), (3 << 3) }, 165 { 37800, (2 << 4), (4 << 3) }, 166 { 44100, (2 << 4), (5 << 3) }, 167 { 33075, (2 << 4), (6 << 3) }, 168 { 6615, (2 << 4), (7 << 3) }, 169 { 0, 0, 0} 170}; 171 172#define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */ 173 174#define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */ 175 176/* Time Slot 3, Serial Port Control register */ 177#define CS4215_XEN (1<<0) /* 0: Enable serial output */ 178#define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */ 179#define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */ 180#define CS4215_BSEL_128 (1<<2) 181#define CS4215_BSEL_256 (2<<2) 182#define CS4215_MCK_MAST (0<<4) /* Master clock */ 183#define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */ 184#define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */ 185#define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */ 186#define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */ 187 188/* Time Slot 4, Test Register */ 189#define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */ 190#define CS4215_ENL (1<<1) /* Enable Loopback Testing */ 191 192/* Time Slot 5, Parallel Port Register */ 193/* Read only here and the same as the in data mode */ 194 195/* Time Slot 6, Reserved */ 196 197/* Time Slot 7, Version Register */ 198#define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */ 199 200/* Time Slot 8, Reserved */ 201 202/* 203 * Data mode 204 */ 205/* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */ 206 207/* Time Slot 5, Output Setting */ 208#define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */ 209#define CS4215_LE (1<<6) /* Line Out Enable */ 210#define CS4215_HE (1<<7) /* Headphone Enable */ 211 212/* Time Slot 6, Output Setting */ 213#define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */ 214#define CS4215_SE (1<<6) /* Speaker Enable */ 215#define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */ 216 217/* Time Slot 7, Input Setting */ 218#define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */ 219#define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */ 220#define CS4215_OVR (1<<5) /* 1: Overrange condition occurred */ 221#define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */ 222#define CS4215_PIO1 (1<<7) 223 224/* Time Slot 8, Input Setting */ 225#define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */ 226#define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */ 227 228/*************************************************************************** 229 DBRI specific definitions and structures 230****************************************************************************/ 231 232/* DBRI main registers */ 233#define REG0 0x00UL /* Status and Control */ 234#define REG1 0x04UL /* Mode and Interrupt */ 235#define REG2 0x08UL /* Parallel IO */ 236#define REG3 0x0cUL /* Test */ 237#define REG8 0x20UL /* Command Queue Pointer */ 238#define REG9 0x24UL /* Interrupt Queue Pointer */ 239 240#define DBRI_NO_CMDS 64 241#define DBRI_INT_BLK 64 242#define DBRI_NO_DESCS 64 243#define DBRI_NO_PIPES 32 244#define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1) 245 246#define DBRI_REC 0 247#define DBRI_PLAY 1 248#define DBRI_NO_STREAMS 2 249 250/* One transmit/receive descriptor */ 251/* When ba != 0 descriptor is used */ 252struct dbri_mem { 253 volatile __u32 word1; 254 __u32 ba; /* Transmit/Receive Buffer Address */ 255 __u32 nda; /* Next Descriptor Address */ 256 volatile __u32 word4; 257}; 258 259/* This structure is in a DMA region where it can accessed by both 260 * the CPU and the DBRI 261 */ 262struct dbri_dma { 263 volatile s32 cmd[DBRI_NO_CMDS]; /* Place for commands */ 264 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */ 265 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */ 266}; 267 268#define dbri_dma_off(member, elem) \ 269 ((u32)(unsigned long) \ 270 (&(((struct dbri_dma *)0)->member[elem]))) 271 272enum in_or_out { PIPEinput, PIPEoutput }; 273 274struct dbri_pipe { 275 u32 sdp; /* SDP command word */ 276 int nextpipe; /* Next pipe in linked list */ 277 int cycle; /* Offset of timeslot (bits) */ 278 int length; /* Length of timeslot (bits) */ 279 int first_desc; /* Index of first descriptor */ 280 int desc; /* Index of active descriptor */ 281 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */ 282}; 283 284/* Per stream (playback or record) information */ 285struct dbri_streaminfo { 286 struct snd_pcm_substream *substream; 287 u32 dvma_buffer; /* Device view of Alsa DMA buffer */ 288 int left; /* # of bytes left in DMA buffer */ 289 int size; /* Size of DMA buffer */ 290 size_t offset; /* offset in user buffer */ 291 int pipe; /* Data pipe used */ 292 int left_gain; /* mixer elements */ 293 int right_gain; 294}; 295 296/* This structure holds the information for both chips (DBRI & CS4215) */ 297struct snd_dbri { 298 struct snd_card *card; /* ALSA card */ 299 300 int regs_size, irq; /* Needed for unload */ 301 struct sbus_dev *sdev; /* SBUS device info */ 302 spinlock_t lock; 303 304 struct dbri_dma *dma; /* Pointer to our DMA block */ 305 u32 dma_dvma; /* DBRI visible DMA address */ 306 307 void __iomem *regs; /* dbri HW regs */ 308 int dbri_irqp; /* intr queue pointer */ 309 int wait_send; /* sequence of command buffers send */ 310 int wait_ackd; /* sequence of command buffers acknowledged */ 311 312 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */ 313 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */ 314 315 int chi_in_pipe; 316 int chi_out_pipe; 317 int chi_bpf; 318 319 struct cs4215 mm; /* mmcodec special info */ 320 /* per stream (playback/record) info */ 321 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS]; 322 323 struct snd_dbri *next; 324}; 325 326#define DBRI_MAX_VOLUME 63 /* Output volume */ 327#define DBRI_MAX_GAIN 15 /* Input gain */ 328 329/* DBRI Reg0 - Status Control Register - defines. (Page 17) */ 330#define D_P (1<<15) /* Program command & queue pointer valid */ 331#define D_G (1<<14) /* Allow 4-Word SBus Burst */ 332#define D_S (1<<13) /* Allow 16-Word SBus Burst */ 333#define D_E (1<<12) /* Allow 8-Word SBus Burst */ 334#define D_X (1<<7) /* Sanity Timer Disable */ 335#define D_T (1<<6) /* Permit activation of the TE interface */ 336#define D_N (1<<5) /* Permit activation of the NT interface */ 337#define D_C (1<<4) /* Permit activation of the CHI interface */ 338#define D_F (1<<3) /* Force Sanity Timer Time-Out */ 339#define D_D (1<<2) /* Disable Master Mode */ 340#define D_H (1<<1) /* Halt for Analysis */ 341#define D_R (1<<0) /* Soft Reset */ 342 343/* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */ 344#define D_LITTLE_END (1<<8) /* Byte Order */ 345#define D_BIG_END (0<<8) /* Byte Order */ 346#define D_MRR (1<<4) /* Multiple Error Ack on SBus (readonly) */ 347#define D_MLE (1<<3) /* Multiple Late Error on SBus (readonly) */ 348#define D_LBG (1<<2) /* Lost Bus Grant on SBus (readonly) */ 349#define D_MBE (1<<1) /* Burst Error on SBus (readonly) */ 350#define D_IR (1<<0) /* Interrupt Indicator (readonly) */ 351 352/* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */ 353#define D_ENPIO3 (1<<7) /* Enable Pin 3 */ 354#define D_ENPIO2 (1<<6) /* Enable Pin 2 */ 355#define D_ENPIO1 (1<<5) /* Enable Pin 1 */ 356#define D_ENPIO0 (1<<4) /* Enable Pin 0 */ 357#define D_ENPIO (0xf0) /* Enable all the pins */ 358#define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */ 359#define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */ 360#define D_PIO1 (1<<1) /* Pin 1: 0: Reset */ 361#define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */ 362 363/* DBRI Commands (Page 20) */ 364#define D_WAIT 0x0 /* Stop execution */ 365#define D_PAUSE 0x1 /* Flush long pipes */ 366#define D_JUMP 0x2 /* New command queue */ 367#define D_IIQ 0x3 /* Initialize Interrupt Queue */ 368#define D_REX 0x4 /* Report command execution via interrupt */ 369#define D_SDP 0x5 /* Setup Data Pipe */ 370#define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */ 371#define D_DTS 0x7 /* Define Time Slot */ 372#define D_SSP 0x8 /* Set short Data Pipe */ 373#define D_CHI 0x9 /* Set CHI Global Mode */ 374#define D_NT 0xa /* NT Command */ 375#define D_TE 0xb /* TE Command */ 376#define D_CDEC 0xc /* Codec setup */ 377#define D_TEST 0xd /* No comment */ 378#define D_CDM 0xe /* CHI Data mode command */ 379 380/* Special bits for some commands */ 381#define D_PIPE(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */ 382 383/* Setup Data Pipe */ 384/* IRM */ 385#define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value rcvd */ 386#define D_SDP_CHANGE (2<<18) /* Report any changes */ 387#define D_SDP_EVERY (3<<18) /* Report any changes */ 388#define D_SDP_EOL (1<<17) /* EOL interrupt enable */ 389#define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */ 390 391/* Pipe data MODE */ 392#define D_SDP_MEM (0<<13) /* To/from memory */ 393#define D_SDP_HDLC (2<<13) 394#define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */ 395#define D_SDP_SER (4<<13) /* Serial to serial */ 396#define D_SDP_FIXED (6<<13) /* Short only */ 397#define D_SDP_MODE(v) ((v)&(7<<13)) 398 399#define D_SDP_TO_SER (1<<12) /* Direction */ 400#define D_SDP_FROM_SER (0<<12) /* Direction */ 401#define D_SDP_MSB (1<<11) /* Bit order within Byte */ 402#define D_SDP_LSB (0<<11) /* Bit order within Byte */ 403#define D_SDP_P (1<<10) /* Pointer Valid */ 404#define D_SDP_A (1<<8) /* Abort */ 405#define D_SDP_C (1<<7) /* Clear */ 406 407/* Define Time Slot */ 408#define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */ 409#define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */ 410#define D_DTS_INS (1<<15) /* Insert Time Slot */ 411#define D_DTS_DEL (0<<15) /* Delete Time Slot */ 412#define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */ 413#define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */ 414 415/* Time Slot defines */ 416#define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */ 417#define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */ 418#define D_TS_DI (1<<13) /* Data Invert */ 419#define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */ 420#define D_TS_MONITOR (2<<10) /* Monitor pipe */ 421#define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */ 422#define D_TS_ANCHOR (7<<10) /* Starting short pipes */ 423#define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */ 424#define D_TS_NEXT(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */ 425 426/* Concentration Highway Interface Modes */ 427#define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */ 428#define D_CHI_IR (1<<15) /* Immediate Interrupt Report */ 429#define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */ 430#define D_CHI_OD (1<<13) /* Open Drain Enable */ 431#define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */ 432#define D_CHI_FD (1<<11) /* Frame Drive */ 433#define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */ 434 435/* NT: These are here for completeness */ 436#define D_NT_FBIT (1<<17) /* Frame Bit */ 437#define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */ 438#define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */ 439#define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */ 440#define D_NT_ISNT (1<<13) /* Configfure interface as NT */ 441#define D_NT_FT (1<<12) /* Fixed Timing */ 442#define D_NT_EZ (1<<11) /* Echo Channel is Zeros */ 443#define D_NT_IFA (1<<10) /* Inhibit Final Activation */ 444#define D_NT_ACT (1<<9) /* Activate Interface */ 445#define D_NT_MFE (1<<8) /* Multiframe Enable */ 446#define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */ 447#define D_NT_LLB(v) ((v)<<2) /* Local Loopback */ 448#define D_NT_FACT (1<<1) /* Force Activation */ 449#define D_NT_ABV (1<<0) /* Activate Bipolar Violation */ 450 451/* Codec Setup */ 452#define D_CDEC_CK(v) ((v)<<24) /* Clock Select */ 453#define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */ 454#define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */ 455 456/* Test */ 457#define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */ 458#define D_TEST_SIZE(v) ((v)<<11) /* */ 459#define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */ 460#define D_TEST_PROC 0x6 /* MicroProcessor test */ 461#define D_TEST_SER 0x7 /* Serial-Controller test */ 462#define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */ 463#define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */ 464#define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */ 465#define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */ 466#define D_TEST_DUMP 0xe /* ROM Dump */ 467 468/* CHI Data Mode */ 469#define D_CDM_THI (1<<8) /* Transmit Data on CHIDR Pin */ 470#define D_CDM_RHI (1<<7) /* Receive Data on CHIDX Pin */ 471#define D_CDM_RCE (1<<6) /* Receive on Rising Edge of CHICK */ 472#define D_CDM_XCE (1<<2) /* Transmit Data on Rising Edge of CHICK */ 473#define D_CDM_XEN (1<<1) /* Transmit Highway Enable */ 474#define D_CDM_REN (1<<0) /* Receive Highway Enable */ 475 476/* The Interrupts */ 477#define D_INTR_BRDY 1 /* Buffer Ready for processing */ 478#define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */ 479#define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */ 480#define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */ 481#define D_INTR_EOL 5 /* End of List */ 482#define D_INTR_CMDI 6 /* Command has bean read */ 483#define D_INTR_XCMP 8 /* Transmission of frame complete */ 484#define D_INTR_SBRI 9 /* BRI status change info */ 485#define D_INTR_FXDT 10 /* Fixed data change */ 486#define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */ 487#define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */ 488#define D_INTR_DBYT 12 /* Dropped by frame slip */ 489#define D_INTR_RBYT 13 /* Repeated by frame slip */ 490#define D_INTR_LINT 14 /* Lost Interrupt */ 491#define D_INTR_UNDR 15 /* DMA underrun */ 492 493#define D_INTR_TE 32 494#define D_INTR_NT 34 495#define D_INTR_CHI 36 496#define D_INTR_CMD 38 497 498#define D_INTR_GETCHAN(v) (((v)>>24) & 0x3f) 499#define D_INTR_GETCODE(v) (((v)>>20) & 0xf) 500#define D_INTR_GETCMD(v) (((v)>>16) & 0xf) 501#define D_INTR_GETVAL(v) ((v) & 0xffff) 502#define D_INTR_GETRVAL(v) ((v) & 0xfffff) 503 504#define D_P_0 0 /* TE receive anchor */ 505#define D_P_1 1 /* TE transmit anchor */ 506#define D_P_2 2 /* NT transmit anchor */ 507#define D_P_3 3 /* NT receive anchor */ 508#define D_P_4 4 /* CHI send data */ 509#define D_P_5 5 /* CHI receive data */ 510#define D_P_6 6 /* */ 511#define D_P_7 7 /* */ 512#define D_P_8 8 /* */ 513#define D_P_9 9 /* */ 514#define D_P_10 10 /* */ 515#define D_P_11 11 /* */ 516#define D_P_12 12 /* */ 517#define D_P_13 13 /* */ 518#define D_P_14 14 /* */ 519#define D_P_15 15 /* */ 520#define D_P_16 16 /* CHI anchor pipe */ 521#define D_P_17 17 /* CHI send */ 522#define D_P_18 18 /* CHI receive */ 523#define D_P_19 19 /* CHI receive */ 524#define D_P_20 20 /* CHI receive */ 525#define D_P_21 21 /* */ 526#define D_P_22 22 /* */ 527#define D_P_23 23 /* */ 528#define D_P_24 24 /* */ 529#define D_P_25 25 /* */ 530#define D_P_26 26 /* */ 531#define D_P_27 27 /* */ 532#define D_P_28 28 /* */ 533#define D_P_29 29 /* */ 534#define D_P_30 30 /* */ 535#define D_P_31 31 /* */ 536 537/* Transmit descriptor defines */ 538#define DBRI_TD_F (1<<31) /* End of Frame */ 539#define DBRI_TD_D (1<<30) /* Do not append CRC */ 540#define DBRI_TD_CNT(v) ((v)<<16) /* Number of valid bytes in the buffer */ 541#define DBRI_TD_B (1<<15) /* Final interrupt */ 542#define DBRI_TD_M (1<<14) /* Marker interrupt */ 543#define DBRI_TD_I (1<<13) /* Transmit Idle Characters */ 544#define DBRI_TD_FCNT(v) (v) /* Flag Count */ 545#define DBRI_TD_UNR (1<<3) /* Underrun: transmitter is out of data */ 546#define DBRI_TD_ABT (1<<2) /* Abort: frame aborted */ 547#define DBRI_TD_TBC (1<<0) /* Transmit buffer Complete */ 548#define DBRI_TD_STATUS(v) ((v)&0xff) /* Transmit status */ 549 /* Maximum buffer size per TD: almost 8Kb */ 550#define DBRI_TD_MAXCNT ((1 << 13) - 1) 551 552/* Receive descriptor defines */ 553#define DBRI_RD_F (1<<31) /* End of Frame */ 554#define DBRI_RD_C (1<<30) /* Completed buffer */ 555#define DBRI_RD_B (1<<15) /* Final interrupt */ 556#define DBRI_RD_M (1<<14) /* Marker interrupt */ 557#define DBRI_RD_BCNT(v) (v) /* Buffer size */ 558#define DBRI_RD_CRC (1<<7) /* 0: CRC is correct */ 559#define DBRI_RD_BBC (1<<6) /* 1: Bad Byte received */ 560#define DBRI_RD_ABT (1<<5) /* Abort: frame aborted */ 561#define DBRI_RD_OVRN (1<<3) /* Overrun: data lost */ 562#define DBRI_RD_STATUS(v) ((v)&0xff) /* Receive status */ 563#define DBRI_RD_CNT(v) (((v)>>16)&0x1fff) /* Valid bytes in the buffer */ 564 565/* stream_info[] access */ 566/* Translate the ALSA direction into the array index */ 567#define DBRI_STREAMNO(substream) \ 568 (substream->stream == \ 569 SNDRV_PCM_STREAM_PLAYBACK? DBRI_PLAY: DBRI_REC) 570 571/* Return a pointer to dbri_streaminfo */ 572#define DBRI_STREAM(dbri, substream) &dbri->stream_info[DBRI_STREAMNO(substream)] 573 574static struct snd_dbri *dbri_list; /* All DBRI devices */ 575 576/* 577 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr. 578 * So we have to reverse the bits. Note: not all bit lengths are supported 579 */ 580static __u32 reverse_bytes(__u32 b, int len) 581{ 582 switch (len) { 583 case 32: 584 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 585 case 16: 586 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 587 case 8: 588 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 589 case 4: 590 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 591 case 2: 592 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 593 case 1: 594 case 0: 595 break; 596 default: 597 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n"); 598 }; 599 600 return b; 601} 602 603/* 604**************************************************************************** 605************** DBRI initialization and command synchronization ************* 606**************************************************************************** 607 608Commands are sent to the DBRI by building a list of them in memory, 609then writing the address of the first list item to DBRI register 8. 610The list is terminated with a WAIT command, which generates a 611CPU interrupt to signal completion. 612 613Since the DBRI can run in parallel with the CPU, several means of 614synchronization present themselves. The method implemented here is close 615to the original scheme (Rudolf's), and uses 2 counters (wait_send and 616wait_ackd) to synchronize the command buffer between the CPU and the DBRI. 617 618A more sophisticated scheme might involve a circular command buffer 619or an array of command buffers. A routine could fill one with 620commands and link it onto a list. When a interrupt signaled 621completion of the current command buffer, look on the list for 622the next one. 623 624Every time a routine wants to write commands to the DBRI, it must 625first call dbri_cmdlock() and get an initial pointer into dbri->dma->cmd 626in return. dbri_cmdlock() will block if the previous commands have not 627been completed yet. After this the commands can be written to the buffer, 628and dbri_cmdsend() is called with the final pointer value to send them 629to the DBRI. 630 631*/ 632 633static void dbri_process_interrupt_buffer(struct snd_dbri * dbri); 634 635enum dbri_lock { NoGetLock, GetLock }; 636#define MAXLOOPS 10 637 638static volatile s32 *dbri_cmdlock(struct snd_dbri * dbri, enum dbri_lock get) 639{ 640 int maxloops = MAXLOOPS; 641 642#ifndef SMP 643 if ((get == GetLock) && spin_is_locked(&dbri->lock)) { 644 printk(KERN_ERR "DBRI: cmdlock called while in spinlock."); 645 } 646#endif 647 648 /* Delay if previous commands are still being processed */ 649 while ((--maxloops) > 0 && (dbri->wait_send != dbri->wait_ackd)) { 650 msleep_interruptible(1); 651 } 652 if (maxloops == 0) { 653 printk(KERN_ERR "DBRI: Chip never completed command buffer %d\n", 654 dbri->wait_send); 655 } else { 656 dprintk(D_CMD, "Chip completed command buffer (%d)\n", 657 MAXLOOPS - maxloops - 1); 658 } 659 660 /*if (get == GetLock) spin_lock(&dbri->lock); */ 661 return &dbri->dma->cmd[0]; 662} 663 664static void dbri_cmdsend(struct snd_dbri * dbri, volatile s32 * cmd) 665{ 666 volatile s32 *ptr; 667 668 for (ptr = &dbri->dma->cmd[0]; ptr < cmd; ptr++) { 669 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr); 670 } 671 672 if ((cmd - &dbri->dma->cmd[0]) >= DBRI_NO_CMDS - 1) { 673 printk(KERN_ERR "DBRI: Command buffer overflow! (bug in driver)\n"); 674 /* Ignore the last part. */ 675 cmd = &dbri->dma->cmd[DBRI_NO_CMDS - 3]; 676 } 677 678 dbri->wait_send++; 679 dbri->wait_send &= 0xffff; /* restrict it to a 16 bit counter. */ 680 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 681 *(cmd++) = DBRI_CMD(D_WAIT, 1, dbri->wait_send); 682 683 /* Set command pointer and signal it is valid. */ 684 sbus_writel(dbri->dma_dvma, dbri->regs + REG8); 685 686 /*spin_unlock(&dbri->lock); */ 687} 688 689/* Lock must be held when calling this */ 690static void dbri_reset(struct snd_dbri * dbri) 691{ 692 int i; 693 694 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n", 695 sbus_readl(dbri->regs + REG0), 696 sbus_readl(dbri->regs + REG2), 697 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9)); 698 699 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */ 700 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++) 701 udelay(10); 702} 703 704/* Lock must not be held before calling this */ 705static void dbri_initialize(struct snd_dbri * dbri) 706{ 707 volatile s32 *cmd; 708 u32 dma_addr, tmp; 709 unsigned long flags; 710 int n; 711 712 spin_lock_irqsave(&dbri->lock, flags); 713 714 dbri_reset(dbri); 715 716 cmd = dbri_cmdlock(dbri, NoGetLock); 717 dprintk(D_GEN, "init: cmd: %p, int: %p\n", 718 &dbri->dma->cmd[0], &dbri->dma->intr[0]); 719 720 /* Initialize pipes */ 721 for (n = 0; n < DBRI_NO_PIPES; n++) 722 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1; 723 724 /* A brute approach - DBRI falls back to working burst size by itself 725 * On SS20 D_S does not work, so do not try so high. */ 726 tmp = sbus_readl(dbri->regs + REG0); 727 tmp |= D_G | D_E; 728 tmp &= ~D_S; 729 sbus_writel(tmp, dbri->regs + REG0); 730 731 /* 732 * Initialize the interrupt ringbuffer. 733 */ 734 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0); 735 dbri->dma->intr[0] = dma_addr; 736 dbri->dbri_irqp = 1; 737 /* 738 * Set up the interrupt queue 739 */ 740 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0); 741 *(cmd++) = dma_addr; 742 743 dbri_cmdsend(dbri, cmd); 744 spin_unlock_irqrestore(&dbri->lock, flags); 745} 746 747/* 748**************************************************************************** 749************************** DBRI data pipe management *********************** 750**************************************************************************** 751 752While DBRI control functions use the command and interrupt buffers, the 753main data path takes the form of data pipes, which can be short (command 754and interrupt driven), or long (attached to DMA buffers). These functions 755provide a rudimentary means of setting up and managing the DBRI's pipes, 756but the calling functions have to make sure they respect the pipes' linked 757list ordering, among other things. The transmit and receive functions 758here interface closely with the transmit and receive interrupt code. 759 760*/ 761static int pipe_active(struct snd_dbri * dbri, int pipe) 762{ 763 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1)); 764} 765 766/* reset_pipe(dbri, pipe) 767 * 768 * Called on an in-use pipe to clear anything being transmitted or received 769 * Lock must be held before calling this. 770 */ 771static void reset_pipe(struct snd_dbri * dbri, int pipe) 772{ 773 int sdp; 774 int desc; 775 volatile int *cmd; 776 777 if (pipe < 0 || pipe > DBRI_MAX_PIPE) { 778 printk(KERN_ERR "DBRI: reset_pipe called with illegal pipe number\n"); 779 return; 780 } 781 782 sdp = dbri->pipes[pipe].sdp; 783 if (sdp == 0) { 784 printk(KERN_ERR "DBRI: reset_pipe called on uninitialized pipe\n"); 785 return; 786 } 787 788 cmd = dbri_cmdlock(dbri, NoGetLock); 789 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P); 790 *(cmd++) = 0; 791 dbri_cmdsend(dbri, cmd); 792 793 desc = dbri->pipes[pipe].first_desc; 794 while (desc != -1) { 795 dbri->dma->desc[desc].nda = dbri->dma->desc[desc].ba = 0; 796 desc = dbri->next_desc[desc]; 797 } 798 799 dbri->pipes[pipe].desc = -1; 800 dbri->pipes[pipe].first_desc = -1; 801} 802 803static void setup_pipe(struct snd_dbri * dbri, int pipe, int sdp) 804{ 805 if (pipe < 0 || pipe > DBRI_MAX_PIPE) { 806 printk(KERN_ERR "DBRI: setup_pipe called with illegal pipe number\n"); 807 return; 808 } 809 810 if ((sdp & 0xf800) != sdp) { 811 printk(KERN_ERR "DBRI: setup_pipe called with strange SDP value\n"); 812 /* sdp &= 0xf800; */ 813 } 814 815 /* If this is a fixed receive pipe, arrange for an interrupt 816 * every time its data changes 817 */ 818 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER)) 819 sdp |= D_SDP_CHANGE; 820 821 sdp |= D_PIPE(pipe); 822 dbri->pipes[pipe].sdp = sdp; 823 dbri->pipes[pipe].desc = -1; 824 dbri->pipes[pipe].first_desc = -1; 825 826 reset_pipe(dbri, pipe); 827} 828 829/* FIXME: direction not needed */ 830static void link_time_slot(struct snd_dbri * dbri, int pipe, 831 enum in_or_out direction, int basepipe, 832 int length, int cycle) 833{ 834 volatile s32 *cmd; 835 int val; 836 int prevpipe; 837 int nextpipe; 838 839 if (pipe < 0 || pipe > DBRI_MAX_PIPE || basepipe < 0 || basepipe > DBRI_MAX_PIPE) { 840 printk(KERN_ERR 841 "DBRI: link_time_slot called with illegal pipe number\n"); 842 return; 843 } 844 845 if (dbri->pipes[pipe].sdp == 0 || dbri->pipes[basepipe].sdp == 0) { 846 printk(KERN_ERR "DBRI: link_time_slot called on uninitialized pipe\n"); 847 return; 848 } 849 850 /* Deal with CHI special case: 851 * "If transmission on edges 0 or 1 is desired, then cycle n 852 * (where n = # of bit times per frame...) must be used." 853 * - DBRI data sheet, page 11 854 */ 855 if (basepipe == 16 && direction == PIPEoutput && cycle == 0) 856 cycle = dbri->chi_bpf; 857 858 if (basepipe == pipe) { 859 prevpipe = pipe; 860 nextpipe = pipe; 861 } else { 862 /* We're not initializing a new linked list (basepipe != pipe), 863 * so run through the linked list and find where this pipe 864 * should be sloted in, based on its cycle. CHI confuses 865 * things a bit, since it has a single anchor for both its 866 * transmit and receive lists. 867 */ 868 if (basepipe == 16) { 869 if (direction == PIPEinput) { 870 prevpipe = dbri->chi_in_pipe; 871 } else { 872 prevpipe = dbri->chi_out_pipe; 873 } 874 } else { 875 prevpipe = basepipe; 876 } 877 878 nextpipe = dbri->pipes[prevpipe].nextpipe; 879 880 while (dbri->pipes[nextpipe].cycle < cycle 881 && dbri->pipes[nextpipe].nextpipe != basepipe) { 882 prevpipe = nextpipe; 883 nextpipe = dbri->pipes[nextpipe].nextpipe; 884 } 885 } 886 887 if (prevpipe == 16) { 888 if (direction == PIPEinput) { 889 dbri->chi_in_pipe = pipe; 890 } else { 891 dbri->chi_out_pipe = pipe; 892 } 893 } else { 894 dbri->pipes[prevpipe].nextpipe = pipe; 895 } 896 897 dbri->pipes[pipe].nextpipe = nextpipe; 898 dbri->pipes[pipe].cycle = cycle; 899 dbri->pipes[pipe].length = length; 900 901 cmd = dbri_cmdlock(dbri, NoGetLock); 902 903 if (direction == PIPEinput) { 904 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe; 905 *(cmd++) = DBRI_CMD(D_DTS, 0, val); 906 *(cmd++) = 907 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe); 908 *(cmd++) = 0; 909 } else { 910 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe; 911 *(cmd++) = DBRI_CMD(D_DTS, 0, val); 912 *(cmd++) = 0; 913 *(cmd++) = 914 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe); 915 } 916 917 dbri_cmdsend(dbri, cmd); 918} 919 920static void unlink_time_slot(struct snd_dbri * dbri, int pipe, 921 enum in_or_out direction, int prevpipe, 922 int nextpipe) 923{ 924 volatile s32 *cmd; 925 int val; 926 927 if (pipe < 0 || pipe > DBRI_MAX_PIPE 928 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE) { 929 printk(KERN_ERR 930 "DBRI: unlink_time_slot called with illegal pipe number\n"); 931 return; 932 } 933 934 cmd = dbri_cmdlock(dbri, NoGetLock); 935 936 if (direction == PIPEinput) { 937 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe; 938 *(cmd++) = DBRI_CMD(D_DTS, 0, val); 939 *(cmd++) = D_TS_NEXT(nextpipe); 940 *(cmd++) = 0; 941 } else { 942 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe; 943 *(cmd++) = DBRI_CMD(D_DTS, 0, val); 944 *(cmd++) = 0; 945 *(cmd++) = D_TS_NEXT(nextpipe); 946 } 947 948 dbri_cmdsend(dbri, cmd); 949} 950 951/* xmit_fixed() / recv_fixed() 952 * 953 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not 954 * expected to change much, and which we don't need to buffer. 955 * The DBRI only interrupts us when the data changes (receive pipes), 956 * or only changes the data when this function is called (transmit pipes). 957 * Only short pipes (numbers 16-31) can be used in fixed data mode. 958 * 959 * These function operate on a 32-bit field, no matter how large 960 * the actual time slot is. The interrupt handler takes care of bit 961 * ordering and alignment. An 8-bit time slot will always end up 962 * in the low-order 8 bits, filled either MSB-first or LSB-first, 963 * depending on the settings passed to setup_pipe() 964 */ 965static void xmit_fixed(struct snd_dbri * dbri, int pipe, unsigned int data) 966{ 967 volatile s32 *cmd; 968 969 if (pipe < 16 || pipe > DBRI_MAX_PIPE) { 970 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n"); 971 return; 972 } 973 974 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) { 975 printk(KERN_ERR "DBRI: xmit_fixed: Uninitialized pipe %d\n", pipe); 976 return; 977 } 978 979 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) { 980 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe); 981 return; 982 } 983 984 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) { 985 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n", pipe); 986 return; 987 } 988 989 /* DBRI short pipes always transmit LSB first */ 990 991 if (dbri->pipes[pipe].sdp & D_SDP_MSB) 992 data = reverse_bytes(data, dbri->pipes[pipe].length); 993 994 cmd = dbri_cmdlock(dbri, GetLock); 995 996 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe); 997 *(cmd++) = data; 998 999 dbri_cmdsend(dbri, cmd); 1000} 1001 1002static void recv_fixed(struct snd_dbri * dbri, int pipe, volatile __u32 * ptr) 1003{ 1004 if (pipe < 16 || pipe > DBRI_MAX_PIPE) { 1005 printk(KERN_ERR "DBRI: recv_fixed called with illegal pipe number\n"); 1006 return; 1007 } 1008 1009 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) { 1010 printk(KERN_ERR "DBRI: recv_fixed called on non-fixed pipe %d\n", pipe); 1011 return; 1012 } 1013 1014 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) { 1015 printk(KERN_ERR "DBRI: recv_fixed called on transmit pipe %d\n", pipe); 1016 return; 1017 } 1018 1019 dbri->pipes[pipe].recv_fixed_ptr = ptr; 1020} 1021 1022/* setup_descs() 1023 * 1024 * Setup transmit/receive data on a "long" pipe - i.e, one associated 1025 * with a DMA buffer. 1026 * 1027 * Only pipe numbers 0-15 can be used in this mode. 1028 * 1029 * This function takes a stream number pointing to a data buffer, 1030 * and work by building chains of descriptors which identify the 1031 * data buffers. Buffers too large for a single descriptor will 1032 * be spread across multiple descriptors. 1033 */ 1034static int setup_descs(struct snd_dbri * dbri, int streamno, unsigned int period) 1035{ 1036 struct dbri_streaminfo *info = &dbri->stream_info[streamno]; 1037 __u32 dvma_buffer; 1038 int desc = 0; 1039 int len; 1040 int first_desc = -1; 1041 int last_desc = -1; 1042 1043 if (info->pipe < 0 || info->pipe > 15) { 1044 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n"); 1045 return -2; 1046 } 1047 1048 if (dbri->pipes[info->pipe].sdp == 0) { 1049 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n", 1050 info->pipe); 1051 return -2; 1052 } 1053 1054 dvma_buffer = info->dvma_buffer; 1055 len = info->size; 1056 1057 if (streamno == DBRI_PLAY) { 1058 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) { 1059 printk(KERN_ERR "DBRI: setup_descs: Called on receive pipe %d\n", 1060 info->pipe); 1061 return -2; 1062 } 1063 } else { 1064 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) { 1065 printk(KERN_ERR 1066 "DBRI: setup_descs: Called on transmit pipe %d\n", 1067 info->pipe); 1068 return -2; 1069 } 1070 /* Should be able to queue multiple buffers to receive on a pipe */ 1071 if (pipe_active(dbri, info->pipe)) { 1072 printk(KERN_ERR "DBRI: recv_on_pipe: Called on active pipe %d\n", 1073 info->pipe); 1074 return -2; 1075 } 1076 1077 /* Make sure buffer size is multiple of four */ 1078 len &= ~3; 1079 } 1080 1081 while (len > 0) { 1082 int mylen; 1083 1084 for (; desc < DBRI_NO_DESCS; desc++) { 1085 if (!dbri->dma->desc[desc].ba) 1086 break; 1087 } 1088 if (desc == DBRI_NO_DESCS) { 1089 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n"); 1090 return -1; 1091 } 1092 1093 if (len > DBRI_TD_MAXCNT) { 1094 mylen = DBRI_TD_MAXCNT; /* 8KB - 1 */ 1095 } else { 1096 mylen = len; 1097 } 1098 if (mylen > period) { 1099 mylen = period; 1100 } 1101 1102 dbri->next_desc[desc] = -1; 1103 dbri->dma->desc[desc].ba = dvma_buffer; 1104 dbri->dma->desc[desc].nda = 0; 1105 1106 if (streamno == DBRI_PLAY) { 1107 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen); 1108 dbri->dma->desc[desc].word4 = 0; 1109 if (first_desc != -1) 1110 dbri->dma->desc[desc].word1 |= DBRI_TD_M; 1111 } else { 1112 dbri->dma->desc[desc].word1 = 0; 1113 dbri->dma->desc[desc].word4 = 1114 DBRI_RD_B | DBRI_RD_BCNT(mylen); 1115 } 1116 1117 if (first_desc == -1) { 1118 first_desc = desc; 1119 } else { 1120 dbri->next_desc[last_desc] = desc; 1121 dbri->dma->desc[last_desc].nda = 1122 dbri->dma_dvma + dbri_dma_off(desc, desc); 1123 } 1124 1125 last_desc = desc; 1126 dvma_buffer += mylen; 1127 len -= mylen; 1128 } 1129 1130 if (first_desc == -1 || last_desc == -1) { 1131 printk(KERN_ERR "DBRI: setup_descs: Not enough descriptors available\n"); 1132 return -1; 1133 } 1134 1135 dbri->dma->desc[last_desc].word1 &= ~DBRI_TD_M; 1136 if (streamno == DBRI_PLAY) { 1137 dbri->dma->desc[last_desc].word1 |= 1138 DBRI_TD_I | DBRI_TD_F | DBRI_TD_B; 1139 } 1140 dbri->pipes[info->pipe].first_desc = first_desc; 1141 dbri->pipes[info->pipe].desc = first_desc; 1142 1143 for (desc = first_desc; desc != -1; desc = dbri->next_desc[desc]) { 1144 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n", 1145 desc, 1146 dbri->dma->desc[desc].word1, 1147 dbri->dma->desc[desc].ba, 1148 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4); 1149 } 1150 return 0; 1151} 1152 1153/* 1154**************************************************************************** 1155************************** DBRI - CHI interface **************************** 1156**************************************************************************** 1157 1158The CHI is a four-wire (clock, frame sync, data in, data out) time-division 1159multiplexed serial interface which the DBRI can operate in either master 1160(give clock/frame sync) or slave (take clock/frame sync) mode. 1161 1162*/ 1163 1164enum master_or_slave { CHImaster, CHIslave }; 1165 1166static void reset_chi(struct snd_dbri * dbri, enum master_or_slave master_or_slave, 1167 int bits_per_frame) 1168{ 1169 volatile s32 *cmd; 1170 int val; 1171 static int chi_initialized = 0; /* FIXME: mutex? */ 1172 1173 if (!chi_initialized) { 1174 1175 cmd = dbri_cmdlock(dbri, GetLock); 1176 1177 /* Set CHI Anchor: Pipe 16 */ 1178 1179 val = D_DTS_VO | D_DTS_VI | D_DTS_INS 1180 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16); 1181 *(cmd++) = DBRI_CMD(D_DTS, 0, val); 1182 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16); 1183 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16); 1184 1185 dbri->pipes[16].sdp = 1; 1186 dbri->pipes[16].nextpipe = 16; 1187 1188#if 0 1189 chi_initialized++; 1190#endif 1191 } else { 1192 int pipe; 1193 1194 for (pipe = dbri->chi_in_pipe; 1195 pipe != 16; pipe = dbri->pipes[pipe].nextpipe) { 1196 unlink_time_slot(dbri, pipe, PIPEinput, 1197 16, dbri->pipes[pipe].nextpipe); 1198 } 1199 for (pipe = dbri->chi_out_pipe; 1200 pipe != 16; pipe = dbri->pipes[pipe].nextpipe) { 1201 unlink_time_slot(dbri, pipe, PIPEoutput, 1202 16, dbri->pipes[pipe].nextpipe); 1203 } 1204 1205 cmd = dbri_cmdlock(dbri, GetLock); 1206 } 1207 dbri->chi_in_pipe = 16; 1208 dbri->chi_out_pipe = 16; 1209 1210 if (master_or_slave == CHIslave) { 1211 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS) 1212 * 1213 * CHICM = 0 (slave mode, 8 kHz frame rate) 1214 * IR = give immediate CHI status interrupt 1215 * EN = give CHI status interrupt upon change 1216 */ 1217 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0)); 1218 } else { 1219 /* Setup DBRI for CHI Master - generate clock, FS 1220 * 1221 * BPF = bits per 8 kHz frame 1222 * 12.288 MHz / CHICM_divisor = clock rate 1223 * FD = 1 - drive CHIFS on rising edge of CHICK 1224 */ 1225 int clockrate = bits_per_frame * 8; 1226 int divisor = 12288 / clockrate; 1227 1228 if (divisor > 255 || divisor * clockrate != 12288) 1229 printk(KERN_ERR "DBRI: illegal bits_per_frame in setup_chi\n"); 1230 1231 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD 1232 | D_CHI_BPF(bits_per_frame)); 1233 } 1234 1235 dbri->chi_bpf = bits_per_frame; 1236 1237 /* CHI Data Mode 1238 * 1239 * RCE = 0 - receive on falling edge of CHICK 1240 * XCE = 1 - transmit on rising edge of CHICK 1241 * XEN = 1 - enable transmitter 1242 * REN = 1 - enable receiver 1243 */ 1244 1245 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); 1246 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN); 1247 1248 dbri_cmdsend(dbri, cmd); 1249} 1250 1251/* 1252**************************************************************************** 1253*********************** CS4215 audio codec management ********************** 1254**************************************************************************** 1255 1256In the standard SPARC audio configuration, the CS4215 codec is attached 1257to the DBRI via the CHI interface and few of the DBRI's PIO pins. 1258 1259*/ 1260static void cs4215_setup_pipes(struct snd_dbri * dbri) 1261{ 1262 /* 1263 * Data mode: 1264 * Pipe 4: Send timeslots 1-4 (audio data) 1265 * Pipe 20: Send timeslots 5-8 (part of ctrl data) 1266 * Pipe 6: Receive timeslots 1-4 (audio data) 1267 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via 1268 * interrupt, and the rest of the data (slot 5 and 8) is 1269 * not relevant for us (only for doublechecking). 1270 * 1271 * Control mode: 1272 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly) 1273 * Pipe 18: Receive timeslot 1 (clb). 1274 * Pipe 19: Receive timeslot 7 (version). 1275 */ 1276 1277 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB); 1278 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB); 1279 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB); 1280 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); 1281 1282 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB); 1283 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); 1284 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); 1285} 1286 1287static int cs4215_init_data(struct cs4215 *mm) 1288{ 1289 /* 1290 * No action, memory resetting only. 1291 * 1292 * Data Time Slot 5-8 1293 * Speaker,Line and Headphone enable. Gain set to the half. 1294 * Input is mike. 1295 */ 1296 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE; 1297 mm->data[1] = CS4215_RO(0x20) | CS4215_SE; 1298 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1; 1299 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf); 1300 1301 /* 1302 * Control Time Slot 1-4 1303 * 0: Default I/O voltage scale 1304 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 1305 * 2: Serial enable, CHI master, 128 bits per frame, clock 1 1306 * 3: Tests disabled 1307 */ 1308 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB; 1309 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 1310 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 1311 mm->ctrl[3] = 0; 1312 1313 mm->status = 0; 1314 mm->version = 0xff; 1315 mm->precision = 8; /* For ULAW */ 1316 mm->channels = 2; 1317 1318 return 0; 1319} 1320 1321static void cs4215_setdata(struct snd_dbri * dbri, int muted) 1322{ 1323 if (muted) { 1324 dbri->mm.data[0] |= 63; 1325 dbri->mm.data[1] |= 63; 1326 dbri->mm.data[2] &= ~15; 1327 dbri->mm.data[3] &= ~15; 1328 } else { 1329 /* Start by setting the playback attenuation. */ 1330 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY]; 1331 int left_gain = info->left_gain & 0x3f; 1332 int right_gain = info->right_gain & 0x3f; 1333 1334 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */ 1335 dbri->mm.data[1] &= ~0x3f; 1336 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain); 1337 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain); 1338 1339 /* Now set the recording gain. */ 1340 info = &dbri->stream_info[DBRI_REC]; 1341 left_gain = info->left_gain & 0xf; 1342 right_gain = info->right_gain & 0xf; 1343 dbri->mm.data[2] |= CS4215_LG(left_gain); 1344 dbri->mm.data[3] |= CS4215_RG(right_gain); 1345 } 1346 1347 xmit_fixed(dbri, 20, *(int *)dbri->mm.data); 1348} 1349 1350/* 1351 * Set the CS4215 to data mode. 1352 */ 1353static void cs4215_open(struct snd_dbri * dbri) 1354{ 1355 int data_width; 1356 u32 tmp; 1357 1358 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n", 1359 dbri->mm.channels, dbri->mm.precision); 1360 1361 /* Temporarily mute outputs, and wait 1/8000 sec (125 us) 1362 * to make sure this takes. This avoids clicking noises. 1363 */ 1364 1365 cs4215_setdata(dbri, 1); 1366 udelay(125); 1367 1368 /* 1369 * Data mode: 1370 * Pipe 4: Send timeslots 1-4 (audio data) 1371 * Pipe 20: Send timeslots 5-8 (part of ctrl data) 1372 * Pipe 6: Receive timeslots 1-4 (audio data) 1373 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via 1374 * interrupt, and the rest of the data (slot 5 and 8) is 1375 * not relevant for us (only for doublechecking). 1376 * 1377 * Just like in control mode, the time slots are all offset by eight 1378 * bits. The CS4215, it seems, observes TSIN (the delayed signal) 1379 * even if it's the CHI master. Don't ask me... 1380 */ 1381 tmp = sbus_readl(dbri->regs + REG0); 1382 tmp &= ~(D_C); /* Disable CHI */ 1383 sbus_writel(tmp, dbri->regs + REG0); 1384 1385 /* Switch CS4215 to data mode - set PIO3 to 1 */ 1386 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 | 1387 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2); 1388 1389 reset_chi(dbri, CHIslave, 128); 1390 1391 /* Note: this next doesn't work for 8-bit stereo, because the two 1392 * channels would be on timeslots 1 and 3, with 2 and 4 idle. 1393 * (See CS4215 datasheet Fig 15) 1394 * 1395 * DBRI non-contiguous mode would be required to make this work. 1396 */ 1397 data_width = dbri->mm.channels * dbri->mm.precision; 1398 1399 link_time_slot(dbri, 20, PIPEoutput, 16, 32, dbri->mm.offset + 32); 1400 link_time_slot(dbri, 4, PIPEoutput, 16, data_width, dbri->mm.offset); 1401 link_time_slot(dbri, 6, PIPEinput, 16, data_width, dbri->mm.offset); 1402 link_time_slot(dbri, 21, PIPEinput, 16, 16, dbri->mm.offset + 40); 1403 1404 /* FIXME: enable CHI after _setdata? */ 1405 tmp = sbus_readl(dbri->regs + REG0); 1406 tmp |= D_C; /* Enable CHI */ 1407 sbus_writel(tmp, dbri->regs + REG0); 1408 1409 cs4215_setdata(dbri, 0); 1410} 1411 1412/* 1413 * Send the control information (i.e. audio format) 1414 */ 1415static int cs4215_setctrl(struct snd_dbri * dbri) 1416{ 1417 int i, val; 1418 u32 tmp; 1419 1420 /* FIXME - let the CPU do something useful during these delays */ 1421 1422 /* Temporarily mute outputs, and wait 1/8000 sec (125 us) 1423 * to make sure this takes. This avoids clicking noises. 1424 */ 1425 cs4215_setdata(dbri, 1); 1426 udelay(125); 1427 1428 /* 1429 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait 1430 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec 1431 */ 1432 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2); 1433 sbus_writel(val, dbri->regs + REG2); 1434 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val); 1435 udelay(34); 1436 1437 /* In Control mode, the CS4215 is a slave device, so the DBRI must 1438 * operate as CHI master, supplying clocking and frame synchronization. 1439 * 1440 * In Data mode, however, the CS4215 must be CHI master to insure 1441 * that its data stream is synchronous with its codec. 1442 * 1443 * The upshot of all this? We start by putting the DBRI into master 1444 * mode, program the CS4215 in Control mode, then switch the CS4215 1445 * into Data mode and put the DBRI into slave mode. Various timing 1446 * requirements must be observed along the way. 1447 * 1448 * Oh, and one more thing, on a SPARCStation 20 (and maybe 1449 * others?), the addressing of the CS4215's time slots is 1450 * offset by eight bits, so we add eight to all the "cycle" 1451 * values in the Define Time Slot (DTS) commands. This is 1452 * done in hardware by a TI 248 that delays the DBRI->4215 1453 * frame sync signal by eight clock cycles. Anybody know why? 1454 */ 1455 tmp = sbus_readl(dbri->regs + REG0); 1456 tmp &= ~D_C; /* Disable CHI */ 1457 sbus_writel(tmp, dbri->regs + REG0); 1458 1459 reset_chi(dbri, CHImaster, 128); 1460 1461 /* 1462 * Control mode: 1463 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly) 1464 * Pipe 18: Receive timeslot 1 (clb). 1465 * Pipe 19: Receive timeslot 7 (version). 1466 */ 1467 1468 link_time_slot(dbri, 17, PIPEoutput, 16, 32, dbri->mm.offset); 1469 link_time_slot(dbri, 18, PIPEinput, 16, 8, dbri->mm.offset); 1470 link_time_slot(dbri, 19, PIPEinput, 16, 8, dbri->mm.offset + 48); 1471 1472 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */ 1473 dbri->mm.ctrl[0] &= ~CS4215_CLB; 1474 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl); 1475 1476 tmp = sbus_readl(dbri->regs + REG0); 1477 tmp |= D_C; /* Enable CHI */ 1478 sbus_writel(tmp, dbri->regs + REG0); 1479 1480 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i) { 1481 msleep_interruptible(1); 1482 } 1483 if (i == 0) { 1484 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n", 1485 dbri->mm.status); 1486 return -1; 1487 } 1488 1489 /* Disable changes to our copy of the version number, as we are about 1490 * to leave control mode. 1491 */ 1492 recv_fixed(dbri, 19, NULL); 1493 1494 /* Terminate CS4215 control mode - data sheet says 1495 * "Set CLB=1 and send two more frames of valid control info" 1496 */ 1497 dbri->mm.ctrl[0] |= CS4215_CLB; 1498 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl); 1499 1500 /* Two frames of control info @ 8kHz frame rate = 250 us delay */ 1501 udelay(250); 1502 1503 cs4215_setdata(dbri, 0); 1504 1505 return 0; 1506} 1507 1508/* 1509 * Setup the codec with the sampling rate, audio format and number of 1510 * channels. 1511 * As part of the process we resend the settings for the data 1512 * timeslots as well. 1513 */ 1514static int cs4215_prepare(struct snd_dbri * dbri, unsigned int rate, 1515 snd_pcm_format_t format, unsigned int channels) 1516{ 1517 int freq_idx; 1518 int ret = 0; 1519 1520 /* Lookup index for this rate */ 1521 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) { 1522 if (CS4215_FREQ[freq_idx].freq == rate) 1523 break; 1524 } 1525 if (CS4215_FREQ[freq_idx].freq != rate) { 1526 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate); 1527 return -1; 1528 } 1529 1530 switch (format) { 1531 case SNDRV_PCM_FORMAT_MU_LAW: 1532 dbri->mm.ctrl[1] = CS4215_DFR_ULAW; 1533 dbri->mm.precision = 8; 1534 break; 1535 case SNDRV_PCM_FORMAT_A_LAW: 1536 dbri->mm.ctrl[1] = CS4215_DFR_ALAW; 1537 dbri->mm.precision = 8; 1538 break; 1539 case SNDRV_PCM_FORMAT_U8: 1540 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8; 1541 dbri->mm.precision = 8; 1542 break; 1543 case SNDRV_PCM_FORMAT_S16_BE: 1544 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16; 1545 dbri->mm.precision = 16; 1546 break; 1547 default: 1548 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format); 1549 return -1; 1550 } 1551 1552 /* Add rate parameters */ 1553 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval; 1554 dbri->mm.ctrl[2] = CS4215_XCLK | 1555 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal; 1556 1557 dbri->mm.channels = channels; 1558 /* Stereo bit: 8 bit stereo not working yet. */ 1559 if ((channels > 1) && (dbri->mm.precision == 16)) 1560 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO; 1561 1562 ret = cs4215_setctrl(dbri); 1563 if (ret == 0) 1564 cs4215_open(dbri); /* set codec to data mode */ 1565 1566 return ret; 1567} 1568 1569/* 1570 * 1571 */ 1572static int cs4215_init(struct snd_dbri * dbri) 1573{ 1574 u32 reg2 = sbus_readl(dbri->regs + REG2); 1575 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2); 1576 1577 /* Look for the cs4215 chips */ 1578 if (reg2 & D_PIO2) { 1579 dprintk(D_MM, "Onboard CS4215 detected\n"); 1580 dbri->mm.onboard = 1; 1581 } 1582 if (reg2 & D_PIO0) { 1583 dprintk(D_MM, "Speakerbox detected\n"); 1584 dbri->mm.onboard = 0; 1585 1586 if (reg2 & D_PIO2) { 1587 printk(KERN_INFO "DBRI: Using speakerbox / " 1588 "ignoring onboard mmcodec.\n"); 1589 sbus_writel(D_ENPIO2, dbri->regs + REG2); 1590 } 1591 } 1592 1593 if (!(reg2 & (D_PIO0 | D_PIO2))) { 1594 printk(KERN_ERR "DBRI: no mmcodec found.\n"); 1595 return -EIO; 1596 } 1597 1598 cs4215_setup_pipes(dbri); 1599 1600 cs4215_init_data(&dbri->mm); 1601 1602 /* Enable capture of the status & version timeslots. */ 1603 recv_fixed(dbri, 18, &dbri->mm.status); 1604 recv_fixed(dbri, 19, &dbri->mm.version); 1605 1606 dbri->mm.offset = dbri->mm.onboard ? 0 : 8; 1607 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) { 1608 dprintk(D_MM, "CS4215 failed probe at offset %d\n", 1609 dbri->mm.offset); 1610 return -EIO; 1611 } 1612 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset); 1613 1614 return 0; 1615} 1616 1617/* 1618**************************************************************************** 1619*************************** DBRI interrupt handler ************************* 1620**************************************************************************** 1621 1622The DBRI communicates with the CPU mainly via a circular interrupt 1623buffer. When an interrupt is signaled, the CPU walks through the 1624buffer and calls dbri_process_one_interrupt() for each interrupt word. 1625Complicated interrupts are handled by dedicated functions (which 1626appear first in this file). Any pending interrupts can be serviced by 1627calling dbri_process_interrupt_buffer(), which works even if the CPU's 1628interrupts are disabled. This function is used by dbri_cmdlock() 1629to make sure we're synced up with the chip before each command sequence, 1630even if we're running cli'ed. 1631 1632*/ 1633 1634/* xmit_descs() 1635 * 1636 * Transmit the current TD's for recording/playing, if needed. 1637 * For playback, ALSA has filled the DMA memory with new data (we hope). 1638 */ 1639static void xmit_descs(unsigned long data) 1640{ 1641 struct snd_dbri *dbri = (struct snd_dbri *) data; 1642 struct dbri_streaminfo *info; 1643 volatile s32 *cmd; 1644 unsigned long flags; 1645 int first_td; 1646 1647 if (dbri == NULL) 1648 return; /* Disabled */ 1649 1650 /* First check the recording stream for buffer overflow */ 1651 info = &dbri->stream_info[DBRI_REC]; 1652 spin_lock_irqsave(&dbri->lock, flags); 1653 1654 if ((info->left >= info->size) && (info->pipe >= 0)) { 1655 first_td = dbri->pipes[info->pipe].first_desc; 1656 1657 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td); 1658 1659 /* Stream could be closed by the time we run. */ 1660 if (first_td < 0) { 1661 goto play; 1662 } 1663 1664 cmd = dbri_cmdlock(dbri, NoGetLock); 1665 *(cmd++) = DBRI_CMD(D_SDP, 0, 1666 dbri->pipes[info->pipe].sdp 1667 | D_SDP_P | D_SDP_EVERY | D_SDP_C); 1668 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td); 1669 dbri_cmdsend(dbri, cmd); 1670 1671 /* Reset our admin of the pipe & bytes read. */ 1672 dbri->pipes[info->pipe].desc = first_td; 1673 info->left = 0; 1674 } 1675 1676play: 1677 spin_unlock_irqrestore(&dbri->lock, flags); 1678 1679 /* Now check the playback stream for buffer underflow */ 1680 info = &dbri->stream_info[DBRI_PLAY]; 1681 spin_lock_irqsave(&dbri->lock, flags); 1682 1683 if ((info->left <= 0) && (info->pipe >= 0)) { 1684 first_td = dbri->pipes[info->pipe].first_desc; 1685 1686 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td); 1687 1688 /* Stream could be closed by the time we run. */ 1689 if (first_td < 0) { 1690 spin_unlock_irqrestore(&dbri->lock, flags); 1691 return; 1692 } 1693 1694 cmd = dbri_cmdlock(dbri, NoGetLock); 1695 *(cmd++) = DBRI_CMD(D_SDP, 0, 1696 dbri->pipes[info->pipe].sdp 1697 | D_SDP_P | D_SDP_EVERY | D_SDP_C); 1698 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td); 1699 dbri_cmdsend(dbri, cmd); 1700 1701 /* Reset our admin of the pipe & bytes written. */ 1702 dbri->pipes[info->pipe].desc = first_td; 1703 info->left = info->size; 1704 } 1705 spin_unlock_irqrestore(&dbri->lock, flags); 1706} 1707 1708static DECLARE_TASKLET(xmit_descs_task, xmit_descs, 0); 1709 1710/* transmission_complete_intr() 1711 * 1712 * Called by main interrupt handler when DBRI signals transmission complete 1713 * on a pipe (interrupt triggered by the B bit in a transmit descriptor). 1714 * 1715 * Walks through the pipe's list of transmit buffer descriptors and marks 1716 * them as available. Stops when the first descriptor is found without 1717 * TBC (Transmit Buffer Complete) set, or we've run through them all. 1718 * 1719 * The DMA buffers are not released, but re-used. Since the transmit buffer 1720 * descriptors are not clobbered, they can be re-submitted as is. This is 1721 * done by the xmit_descs() tasklet above since that could take longer. 1722 */ 1723 1724static void transmission_complete_intr(struct snd_dbri * dbri, int pipe) 1725{ 1726 struct dbri_streaminfo *info; 1727 int td; 1728 int status; 1729 int len; 1730 1731 info = &dbri->stream_info[DBRI_PLAY]; 1732 1733 td = dbri->pipes[pipe].desc; 1734 while (td >= 0) { 1735 if (td >= DBRI_NO_DESCS) { 1736 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe); 1737 return; 1738 } 1739 1740 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4); 1741 if (!(status & DBRI_TD_TBC)) { 1742 break; 1743 } 1744 1745 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status); 1746 1747 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */ 1748 len = DBRI_RD_CNT(dbri->dma->desc[td].word1); 1749 info->offset += len; 1750 info->left -= len; 1751 1752 /* On the last TD, transmit them all again. */ 1753 if (dbri->next_desc[td] == -1) { 1754 if (info->left > 0) { 1755 printk(KERN_WARNING 1756 "%d bytes left after last transfer.\n", 1757 info->left); 1758 info->left = 0; 1759 } 1760 tasklet_schedule(&xmit_descs_task); 1761 } 1762 1763 td = dbri->next_desc[td]; 1764 dbri->pipes[pipe].desc = td; 1765 } 1766 1767 /* Notify ALSA */ 1768 if (spin_is_locked(&dbri->lock)) { 1769 spin_unlock(&dbri->lock); 1770 snd_pcm_period_elapsed(info->substream); 1771 spin_lock(&dbri->lock); 1772 } else 1773 snd_pcm_period_elapsed(info->substream); 1774} 1775 1776static void reception_complete_intr(struct snd_dbri * dbri, int pipe) 1777{ 1778 struct dbri_streaminfo *info; 1779 int rd = dbri->pipes[pipe].desc; 1780 s32 status; 1781 1782 if (rd < 0 || rd >= DBRI_NO_DESCS) { 1783 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe); 1784 return; 1785 } 1786 1787 dbri->dma->desc[rd].ba = 0; 1788 dbri->pipes[pipe].desc = dbri->next_desc[rd]; 1789 status = dbri->dma->desc[rd].word1; 1790 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */ 1791 1792 info = &dbri->stream_info[DBRI_REC]; 1793 info->offset += DBRI_RD_CNT(status); 1794 info->left += DBRI_RD_CNT(status); 1795 1796 /* FIXME: Check status */ 1797 1798 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n", 1799 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status)); 1800 1801 /* On the last TD, transmit them all again. */ 1802 if (dbri->next_desc[rd] == -1) { 1803 if (info->left > info->size) { 1804 printk(KERN_WARNING 1805 "%d bytes recorded in %d size buffer.\n", 1806 info->left, info->size); 1807 } 1808 tasklet_schedule(&xmit_descs_task); 1809 } 1810 1811 /* Notify ALSA */ 1812 if (spin_is_locked(&dbri->lock)) { 1813 spin_unlock(&dbri->lock); 1814 snd_pcm_period_elapsed(info->substream); 1815 spin_lock(&dbri->lock); 1816 } else 1817 snd_pcm_period_elapsed(info->substream); 1818} 1819 1820static void dbri_process_one_interrupt(struct snd_dbri * dbri, int x) 1821{ 1822 int val = D_INTR_GETVAL(x); 1823 int channel = D_INTR_GETCHAN(x); 1824 int command = D_INTR_GETCMD(x); 1825 int code = D_INTR_GETCODE(x); 1826#ifdef DBRI_DEBUG 1827 int rval = D_INTR_GETRVAL(x); 1828#endif 1829 1830 if (channel == D_INTR_CMD) { 1831 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n", 1832 cmds[command], val); 1833 } else { 1834 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n", 1835 channel, code, rval); 1836 } 1837 1838 if (channel == D_INTR_CMD && command == D_WAIT) { 1839 dbri->wait_ackd = val; 1840 if (dbri->wait_send != val) { 1841 printk(KERN_ERR "Processing wait command %d when %d was send.\n", 1842 val, dbri->wait_send); 1843 } 1844 return; 1845 } 1846 1847 switch (code) { 1848 case D_INTR_BRDY: 1849 reception_complete_intr(dbri, channel); 1850 break; 1851 case D_INTR_XCMP: 1852 case D_INTR_MINT: 1853 transmission_complete_intr(dbri, channel); 1854 break; 1855 case D_INTR_UNDR: 1856 /* UNDR - Transmission underrun 1857 * resend SDP command with clear pipe bit (C) set 1858 */ 1859 { 1860 volatile s32 *cmd; 1861 1862 int pipe = channel; 1863 int td = dbri->pipes[pipe].desc; 1864 1865 dbri->dma->desc[td].word4 = 0; 1866 cmd = dbri_cmdlock(dbri, NoGetLock); 1867 *(cmd++) = DBRI_CMD(D_SDP, 0, 1868 dbri->pipes[pipe].sdp 1869 | D_SDP_P | D_SDP_C | D_SDP_2SAME); 1870 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td); 1871 dbri_cmdsend(dbri, cmd); 1872 } 1873 break; 1874 case D_INTR_FXDT: 1875 /* FXDT - Fixed data change */ 1876 if (dbri->pipes[channel].sdp & D_SDP_MSB) 1877 val = reverse_bytes(val, dbri->pipes[channel].length); 1878 1879 if (dbri->pipes[channel].recv_fixed_ptr) 1880 *(dbri->pipes[channel].recv_fixed_ptr) = val; 1881 break; 1882 default: 1883 if (channel != D_INTR_CMD) 1884 printk(KERN_WARNING 1885 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x); 1886 } 1887} 1888 1889/* dbri_process_interrupt_buffer advances through the DBRI's interrupt 1890 * buffer until it finds a zero word (indicating nothing more to do 1891 * right now). Non-zero words require processing and are handed off 1892 * to dbri_process_one_interrupt AFTER advancing the pointer. This 1893 * order is important since we might recurse back into this function 1894 * and need to make sure the pointer has been advanced first. 1895 */ 1896static void dbri_process_interrupt_buffer(struct snd_dbri * dbri) 1897{ 1898 s32 x; 1899 1900 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) { 1901 dbri->dma->intr[dbri->dbri_irqp] = 0; 1902 dbri->dbri_irqp++; 1903 if (dbri->dbri_irqp == DBRI_INT_BLK) 1904 dbri->dbri_irqp = 1; 1905 1906 dbri_process_one_interrupt(dbri, x); 1907 } 1908} 1909 1910static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id, 1911 struct pt_regs *regs) 1912{ 1913 struct snd_dbri *dbri = dev_id; 1914 static int errcnt = 0; 1915 int x; 1916 1917 if (dbri == NULL) 1918 return IRQ_NONE; 1919 spin_lock(&dbri->lock); 1920 1921 /* 1922 * Read it, so the interrupt goes away. 1923 */ 1924 x = sbus_readl(dbri->regs + REG1); 1925 1926 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) { 1927 u32 tmp; 1928 1929 if (x & D_MRR) 1930 printk(KERN_ERR 1931 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n", 1932 x); 1933 if (x & D_MLE) 1934 printk(KERN_ERR 1935 "DBRI: Multiple Late Error on SBus reg1=0x%x\n", 1936 x); 1937 if (x & D_LBG) 1938 printk(KERN_ERR 1939 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x); 1940 if (x & D_MBE) 1941 printk(KERN_ERR 1942 "DBRI: Burst Error on SBus reg1=0x%x\n", x); 1943 1944 /* Some of these SBus errors cause the chip's SBus circuitry 1945 * to be disabled, so just re-enable and try to keep going. 1946 * 1947 * The only one I've seen is MRR, which will be triggered 1948 * if you let a transmit pipe underrun, then try to CDP it. 1949 * 1950 * If these things persist, we reset the chip. 1951 */ 1952 if ((++errcnt) % 10 == 0) { 1953 dprintk(D_INT, "Interrupt errors exceeded.\n"); 1954 dbri_reset(dbri); 1955 } else { 1956 tmp = sbus_readl(dbri->regs + REG0); 1957 tmp &= ~(D_D); 1958 sbus_writel(tmp, dbri->regs + REG0); 1959 } 1960 } 1961 1962 dbri_process_interrupt_buffer(dbri); 1963 1964 /* FIXME: Write 0 into regs to ACK interrupt */ 1965 1966 spin_unlock(&dbri->lock); 1967 1968 return IRQ_HANDLED; 1969} 1970 1971/**************************************************************************** 1972 PCM Interface 1973****************************************************************************/ 1974static struct snd_pcm_hardware snd_dbri_pcm_hw = { 1975 .info = (SNDRV_PCM_INFO_MMAP | 1976 SNDRV_PCM_INFO_INTERLEAVED | 1977 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1978 SNDRV_PCM_INFO_MMAP_VALID), 1979 .formats = SNDRV_PCM_FMTBIT_MU_LAW | 1980 SNDRV_PCM_FMTBIT_A_LAW | 1981 SNDRV_PCM_FMTBIT_U8 | 1982 SNDRV_PCM_FMTBIT_S16_BE, 1983 .rates = SNDRV_PCM_RATE_8000_48000, 1984 .rate_min = 8000, 1985 .rate_max = 48000, 1986 .channels_min = 1, 1987 .channels_max = 2, 1988 .buffer_bytes_max = (64 * 1024), 1989 .period_bytes_min = 1, 1990 .period_bytes_max = DBRI_TD_MAXCNT, 1991 .periods_min = 1, 1992 .periods_max = 1024, 1993}; 1994 1995static int snd_dbri_open(struct snd_pcm_substream *substream) 1996{ 1997 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 1998 struct snd_pcm_runtime *runtime = substream->runtime; 1999 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2000 unsigned long flags; 2001 2002 dprintk(D_USR, "open audio output.\n"); 2003 runtime->hw = snd_dbri_pcm_hw; 2004 2005 spin_lock_irqsave(&dbri->lock, flags); 2006 info->substream = substream; 2007 info->left = 0; 2008 info->offset = 0; 2009 info->dvma_buffer = 0; 2010 info->pipe = -1; 2011 spin_unlock_irqrestore(&dbri->lock, flags); 2012 2013 cs4215_open(dbri); 2014 2015 return 0; 2016} 2017 2018static int snd_dbri_close(struct snd_pcm_substream *substream) 2019{ 2020 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2021 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2022 2023 dprintk(D_USR, "close audio output.\n"); 2024 info->substream = NULL; 2025 info->left = 0; 2026 info->offset = 0; 2027 2028 return 0; 2029} 2030 2031static int snd_dbri_hw_params(struct snd_pcm_substream *substream, 2032 struct snd_pcm_hw_params *hw_params) 2033{ 2034 struct snd_pcm_runtime *runtime = substream->runtime; 2035 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2036 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2037 int direction; 2038 int ret; 2039 2040 /* set sampling rate, audio format and number of channels */ 2041 ret = cs4215_prepare(dbri, params_rate(hw_params), 2042 params_format(hw_params), 2043 params_channels(hw_params)); 2044 if (ret != 0) 2045 return ret; 2046 2047 if ((ret = snd_pcm_lib_malloc_pages(substream, 2048 params_buffer_bytes(hw_params))) < 0) { 2049 printk(KERN_ERR "malloc_pages failed with %d\n", ret); 2050 return ret; 2051 } 2052 2053 /* hw_params can get called multiple times. Only map the DMA once. 2054 */ 2055 if (info->dvma_buffer == 0) { 2056 if (DBRI_STREAMNO(substream) == DBRI_PLAY) 2057 direction = SBUS_DMA_TODEVICE; 2058 else 2059 direction = SBUS_DMA_FROMDEVICE; 2060 2061 info->dvma_buffer = sbus_map_single(dbri->sdev, 2062 runtime->dma_area, 2063 params_buffer_bytes(hw_params), 2064 direction); 2065 } 2066 2067 direction = params_buffer_bytes(hw_params); 2068 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n", 2069 direction, info->dvma_buffer); 2070 return 0; 2071} 2072 2073static int snd_dbri_hw_free(struct snd_pcm_substream *substream) 2074{ 2075 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2076 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2077 int direction; 2078 dprintk(D_USR, "hw_free.\n"); 2079 2080 /* hw_free can get called multiple times. Only unmap the DMA once. 2081 */ 2082 if (info->dvma_buffer) { 2083 if (DBRI_STREAMNO(substream) == DBRI_PLAY) 2084 direction = SBUS_DMA_TODEVICE; 2085 else 2086 direction = SBUS_DMA_FROMDEVICE; 2087 2088 sbus_unmap_single(dbri->sdev, info->dvma_buffer, 2089 substream->runtime->buffer_size, direction); 2090 info->dvma_buffer = 0; 2091 } 2092 info->pipe = -1; 2093 2094 return snd_pcm_lib_free_pages(substream); 2095} 2096 2097static int snd_dbri_prepare(struct snd_pcm_substream *substream) 2098{ 2099 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2100 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2101 struct snd_pcm_runtime *runtime = substream->runtime; 2102 int ret; 2103 2104 info->size = snd_pcm_lib_buffer_bytes(substream); 2105 if (DBRI_STREAMNO(substream) == DBRI_PLAY) 2106 info->pipe = 4; /* Send pipe */ 2107 else { 2108 info->pipe = 6; /* Receive pipe */ 2109 info->left = info->size; /* To trigger submittal */ 2110 } 2111 2112 spin_lock_irq(&dbri->lock); 2113 2114 /* Setup the all the transmit/receive desciptors to cover the 2115 * whole DMA buffer. 2116 */ 2117 ret = setup_descs(dbri, DBRI_STREAMNO(substream), 2118 snd_pcm_lib_period_bytes(substream)); 2119 2120 runtime->stop_threshold = DBRI_TD_MAXCNT / runtime->channels; 2121 2122 spin_unlock_irq(&dbri->lock); 2123 2124 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size); 2125 return ret; 2126} 2127 2128static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd) 2129{ 2130 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2131 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2132 int ret = 0; 2133 2134 switch (cmd) { 2135 case SNDRV_PCM_TRIGGER_START: 2136 dprintk(D_USR, "start audio, period is %d bytes\n", 2137 (int)snd_pcm_lib_period_bytes(substream)); 2138 /* Enable & schedule the tasklet that re-submits the TDs. */ 2139 xmit_descs_task.data = (unsigned long)dbri; 2140 tasklet_schedule(&xmit_descs_task); 2141 break; 2142 case SNDRV_PCM_TRIGGER_STOP: 2143 dprintk(D_USR, "stop audio.\n"); 2144 /* Make the tasklet bail out immediately. */ 2145 xmit_descs_task.data = 0; 2146 reset_pipe(dbri, info->pipe); 2147 break; 2148 default: 2149 ret = -EINVAL; 2150 } 2151 2152 return ret; 2153} 2154 2155static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream) 2156{ 2157 struct snd_dbri *dbri = snd_pcm_substream_chip(substream); 2158 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); 2159 snd_pcm_uframes_t ret; 2160 2161 ret = bytes_to_frames(substream->runtime, info->offset) 2162 % substream->runtime->buffer_size; 2163 dprintk(D_USR, "I/O pointer: %ld frames, %d bytes left.\n", 2164 ret, info->left); 2165 return ret; 2166} 2167 2168static struct snd_pcm_ops snd_dbri_ops = { 2169 .open = snd_dbri_open, 2170 .close = snd_dbri_close, 2171 .ioctl = snd_pcm_lib_ioctl, 2172 .hw_params = snd_dbri_hw_params, 2173 .hw_free = snd_dbri_hw_free, 2174 .prepare = snd_dbri_prepare, 2175 .trigger = snd_dbri_trigger, 2176 .pointer = snd_dbri_pointer, 2177}; 2178 2179static int __devinit snd_dbri_pcm(struct snd_dbri * dbri) 2180{ 2181 struct snd_pcm *pcm; 2182 int err; 2183 2184 if ((err = snd_pcm_new(dbri->card, 2185 /* ID */ "sun_dbri", 2186 /* device */ 0, 2187 /* playback count */ 1, 2188 /* capture count */ 1, &pcm)) < 0) 2189 return err; 2190 snd_assert(pcm != NULL, return -EINVAL); 2191 2192 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops); 2193 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops); 2194 2195 pcm->private_data = dbri; 2196 pcm->info_flags = 0; 2197 strcpy(pcm->name, dbri->card->shortname); 2198 2199 if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm, 2200 SNDRV_DMA_TYPE_CONTINUOUS, 2201 snd_dma_continuous_data(GFP_KERNEL), 2202 64 * 1024, 64 * 1024)) < 0) { 2203 return err; 2204 } 2205 2206 return 0; 2207} 2208 2209/***************************************************************************** 2210 Mixer interface 2211*****************************************************************************/ 2212 2213static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol, 2214 struct snd_ctl_elem_info *uinfo) 2215{ 2216 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2217 uinfo->count = 2; 2218 uinfo->value.integer.min = 0; 2219 if (kcontrol->private_value == DBRI_PLAY) { 2220 uinfo->value.integer.max = DBRI_MAX_VOLUME; 2221 } else { 2222 uinfo->value.integer.max = DBRI_MAX_GAIN; 2223 } 2224 return 0; 2225} 2226 2227static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol, 2228 struct snd_ctl_elem_value *ucontrol) 2229{ 2230 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); 2231 struct dbri_streaminfo *info; 2232 snd_assert(dbri != NULL, return -EINVAL); 2233 info = &dbri->stream_info[kcontrol->private_value]; 2234 snd_assert(info != NULL, return -EINVAL); 2235 2236 ucontrol->value.integer.value[0] = info->left_gain; 2237 ucontrol->value.integer.value[1] = info->right_gain; 2238 return 0; 2239} 2240 2241static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol, 2242 struct snd_ctl_elem_value *ucontrol) 2243{ 2244 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); 2245 struct dbri_streaminfo *info = &dbri->stream_info[kcontrol->private_value]; 2246 unsigned long flags; 2247 int changed = 0; 2248 2249 if (info->left_gain != ucontrol->value.integer.value[0]) { 2250 info->left_gain = ucontrol->value.integer.value[0]; 2251 changed = 1; 2252 } 2253 if (info->right_gain != ucontrol->value.integer.value[1]) { 2254 info->right_gain = ucontrol->value.integer.value[1]; 2255 changed = 1; 2256 } 2257 if (changed == 1) { 2258 /* First mute outputs, and wait 1/8000 sec (125 us) 2259 * to make sure this takes. This avoids clicking noises. 2260 */ 2261 spin_lock_irqsave(&dbri->lock, flags); 2262 2263 cs4215_setdata(dbri, 1); 2264 udelay(125); 2265 cs4215_setdata(dbri, 0); 2266 2267 spin_unlock_irqrestore(&dbri->lock, flags); 2268 } 2269 return changed; 2270} 2271 2272static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol, 2273 struct snd_ctl_elem_info *uinfo) 2274{ 2275 int mask = (kcontrol->private_value >> 16) & 0xff; 2276 2277 uinfo->type = (mask == 1) ? 2278 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 2279 uinfo->count = 1; 2280 uinfo->value.integer.min = 0; 2281 uinfo->value.integer.max = mask; 2282 return 0; 2283} 2284 2285static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol, 2286 struct snd_ctl_elem_value *ucontrol) 2287{ 2288 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); 2289 int elem = kcontrol->private_value & 0xff; 2290 int shift = (kcontrol->private_value >> 8) & 0xff; 2291 int mask = (kcontrol->private_value >> 16) & 0xff; 2292 int invert = (kcontrol->private_value >> 24) & 1; 2293 snd_assert(dbri != NULL, return -EINVAL); 2294 2295 if (elem < 4) { 2296 ucontrol->value.integer.value[0] = 2297 (dbri->mm.data[elem] >> shift) & mask; 2298 } else { 2299 ucontrol->value.integer.value[0] = 2300 (dbri->mm.ctrl[elem - 4] >> shift) & mask; 2301 } 2302 2303 if (invert == 1) { 2304 ucontrol->value.integer.value[0] = 2305 mask - ucontrol->value.integer.value[0]; 2306 } 2307 return 0; 2308} 2309 2310static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol, 2311 struct snd_ctl_elem_value *ucontrol) 2312{ 2313 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); 2314 unsigned long flags; 2315 int elem = kcontrol->private_value & 0xff; 2316 int shift = (kcontrol->private_value >> 8) & 0xff; 2317 int mask = (kcontrol->private_value >> 16) & 0xff; 2318 int invert = (kcontrol->private_value >> 24) & 1; 2319 int changed = 0; 2320 unsigned short val; 2321 snd_assert(dbri != NULL, return -EINVAL); 2322 2323 val = (ucontrol->value.integer.value[0] & mask); 2324 if (invert == 1) 2325 val = mask - val; 2326 val <<= shift; 2327 2328 if (elem < 4) { 2329 dbri->mm.data[elem] = (dbri->mm.data[elem] & 2330 ~(mask << shift)) | val; 2331 changed = (val != dbri->mm.data[elem]); 2332 } else { 2333 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] & 2334 ~(mask << shift)) | val; 2335 changed = (val != dbri->mm.ctrl[elem - 4]); 2336 } 2337 2338 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, " 2339 "mixer-value=%ld, mm-value=0x%x\n", 2340 mask, changed, ucontrol->value.integer.value[0], 2341 dbri->mm.data[elem & 3]); 2342 2343 if (changed) { 2344 /* First mute outputs, and wait 1/8000 sec (125 us) 2345 * to make sure this takes. This avoids clicking noises. 2346 */ 2347 spin_lock_irqsave(&dbri->lock, flags); 2348 2349 cs4215_setdata(dbri, 1); 2350 udelay(125); 2351 cs4215_setdata(dbri, 0); 2352 2353 spin_unlock_irqrestore(&dbri->lock, flags); 2354 } 2355 return changed; 2356} 2357 2358/* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control 2359 timeslots. Shift is the bit offset in the timeslot, mask defines the 2360 number of bits. invert is a boolean for use with attenuation. 2361 */ 2362#define CS4215_SINGLE(xname, entry, shift, mask, invert) \ 2363{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2364 .info = snd_cs4215_info_single, \ 2365 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \ 2366 .private_value = entry | (shift << 8) | (mask << 16) | (invert << 24) }, 2367 2368static struct snd_kcontrol_new dbri_controls[] __devinitdata = { 2369 { 2370 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2371 .name = "Playback Volume", 2372 .info = snd_cs4215_info_volume, 2373 .get = snd_cs4215_get_volume, 2374 .put = snd_cs4215_put_volume, 2375 .private_value = DBRI_PLAY, 2376 }, 2377 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0) 2378 CS4215_SINGLE("Line out switch", 0, 6, 1, 0) 2379 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0) 2380 { 2381 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2382 .name = "Capture Volume", 2383 .info = snd_cs4215_info_volume, 2384 .get = snd_cs4215_get_volume, 2385 .put = snd_cs4215_put_volume, 2386 .private_value = DBRI_REC, 2387 }, 2388 /* FIXME: mic/line switch */ 2389 CS4215_SINGLE("Line in switch", 2, 4, 1, 0) 2390 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0) 2391 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1) 2392 CS4215_SINGLE("Mic boost", 4, 4, 1, 1) 2393}; 2394 2395#define NUM_CS4215_CONTROLS (sizeof(dbri_controls)/sizeof(struct snd_kcontrol_new)) 2396 2397static int __init snd_dbri_mixer(struct snd_dbri * dbri) 2398{ 2399 struct snd_card *card; 2400 int idx, err; 2401 2402 snd_assert(dbri != NULL && dbri->card != NULL, return -EINVAL); 2403 2404 card = dbri->card; 2405 strcpy(card->mixername, card->shortname); 2406 2407 for (idx = 0; idx < NUM_CS4215_CONTROLS; idx++) { 2408 if ((err = snd_ctl_add(card, 2409 snd_ctl_new1(&dbri_controls[idx], dbri))) < 0) 2410 return err; 2411 } 2412 2413 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) { 2414 dbri->stream_info[idx].left_gain = 0; 2415 dbri->stream_info[idx].right_gain = 0; 2416 } 2417 2418 return 0; 2419} 2420 2421/**************************************************************************** 2422 /proc interface 2423****************************************************************************/ 2424static void dbri_regs_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer) 2425{ 2426 struct snd_dbri *dbri = entry->private_data; 2427 2428 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0)); 2429 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2)); 2430 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8)); 2431 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9)); 2432} 2433 2434#ifdef DBRI_DEBUG 2435static void dbri_debug_read(struct snd_info_entry * entry, 2436 struct snd_info_buffer *buffer) 2437{ 2438 struct snd_dbri *dbri = entry->private_data; 2439 int pipe; 2440 snd_iprintf(buffer, "debug=%d\n", dbri_debug); 2441 2442 for (pipe = 0; pipe < 32; pipe++) { 2443 if (pipe_active(dbri, pipe)) { 2444 struct dbri_pipe *pptr = &dbri->pipes[pipe]; 2445 snd_iprintf(buffer, 2446 "Pipe %d: %s SDP=0x%x desc=%d, " 2447 "len=%d @ %d next %d\n", 2448 pipe, 2449 ((pptr->sdp & D_SDP_TO_SER) ? "output" : "input"), 2450 pptr->sdp, pptr->desc, 2451 pptr->length, pptr->cycle, pptr->nextpipe); 2452 } 2453 } 2454} 2455#endif 2456 2457void snd_dbri_proc(struct snd_dbri * dbri) 2458{ 2459 struct snd_info_entry *entry; 2460 2461 if (! snd_card_proc_new(dbri->card, "regs", &entry)) 2462 snd_info_set_text_ops(entry, dbri, dbri_regs_read); 2463 2464#ifdef DBRI_DEBUG 2465 if (! snd_card_proc_new(dbri->card, "debug", &entry)) { 2466 snd_info_set_text_ops(entry, dbri, dbri_debug_read); 2467 entry->mode = S_IFREG | S_IRUGO; /* Readable only. */ 2468 } 2469#endif 2470} 2471 2472/* 2473**************************************************************************** 2474**************************** Initialization ******************************** 2475**************************************************************************** 2476*/ 2477static void snd_dbri_free(struct snd_dbri * dbri); 2478 2479static int __init snd_dbri_create(struct snd_card *card, 2480 struct sbus_dev *sdev, 2481 struct linux_prom_irqs *irq, int dev) 2482{ 2483 struct snd_dbri *dbri = card->private_data; 2484 int err; 2485 2486 spin_lock_init(&dbri->lock); 2487 dbri->card = card; 2488 dbri->sdev = sdev; 2489 dbri->irq = irq->pri; 2490 2491 dbri->dma = sbus_alloc_consistent(sdev, sizeof(struct dbri_dma), 2492 &dbri->dma_dvma); 2493 memset((void *)dbri->dma, 0, sizeof(struct dbri_dma)); 2494 2495 dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n", 2496 dbri->dma, dbri->dma_dvma); 2497 2498 /* Map the registers into memory. */ 2499 dbri->regs_size = sdev->reg_addrs[0].reg_size; 2500 dbri->regs = sbus_ioremap(&sdev->resource[0], 0, 2501 dbri->regs_size, "DBRI Registers"); 2502 if (!dbri->regs) { 2503 printk(KERN_ERR "DBRI: could not allocate registers\n"); 2504 sbus_free_consistent(sdev, sizeof(struct dbri_dma), 2505 (void *)dbri->dma, dbri->dma_dvma); 2506 return -EIO; 2507 } 2508 2509 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED, 2510 "DBRI audio", dbri); 2511 if (err) { 2512 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq); 2513 sbus_iounmap(dbri->regs, dbri->regs_size); 2514 sbus_free_consistent(sdev, sizeof(struct dbri_dma), 2515 (void *)dbri->dma, dbri->dma_dvma); 2516 return err; 2517 } 2518 2519 /* Do low level initialization of the DBRI and CS4215 chips */ 2520 dbri_initialize(dbri); 2521 err = cs4215_init(dbri); 2522 if (err) { 2523 snd_dbri_free(dbri); 2524 return err; 2525 } 2526 2527 dbri->next = dbri_list; 2528 dbri_list = dbri; 2529 2530 return 0; 2531} 2532 2533static void snd_dbri_free(struct snd_dbri * dbri) 2534{ 2535 dprintk(D_GEN, "snd_dbri_free\n"); 2536 dbri_reset(dbri); 2537 2538 if (dbri->irq) 2539 free_irq(dbri->irq, dbri); 2540 2541 if (dbri->regs) 2542 sbus_iounmap(dbri->regs, dbri->regs_size); 2543 2544 if (dbri->dma) 2545 sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma), 2546 (void *)dbri->dma, dbri->dma_dvma); 2547} 2548 2549static int __init dbri_attach(int prom_node, struct sbus_dev *sdev) 2550{ 2551 struct snd_dbri *dbri; 2552 struct linux_prom_irqs irq; 2553 struct resource *rp; 2554 struct snd_card *card; 2555 static int dev = 0; 2556 int err; 2557 2558 if (sdev->prom_name[9] < 'e') { 2559 printk(KERN_ERR "DBRI: unsupported chip version %c found.\n", 2560 sdev->prom_name[9]); 2561 return -EIO; 2562 } 2563 2564 if (dev >= SNDRV_CARDS) 2565 return -ENODEV; 2566 if (!enable[dev]) { 2567 dev++; 2568 return -ENOENT; 2569 } 2570 2571 err = prom_getproperty(prom_node, "intr", (char *)&irq, sizeof(irq)); 2572 if (err < 0) { 2573 printk(KERN_ERR "DBRI-%d: Firmware node lacks IRQ property.\n", dev); 2574 return -ENODEV; 2575 } 2576 2577 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 2578 sizeof(struct snd_dbri)); 2579 if (card == NULL) 2580 return -ENOMEM; 2581 2582 strcpy(card->driver, "DBRI"); 2583 strcpy(card->shortname, "Sun DBRI"); 2584 rp = &sdev->resource[0]; 2585 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d", 2586 card->shortname, 2587 rp->flags & 0xffL, (unsigned long long)rp->start, irq.pri); 2588 2589 if ((err = snd_dbri_create(card, sdev, &irq, dev)) < 0) { 2590 snd_card_free(card); 2591 return err; 2592 } 2593 2594 dbri = card->private_data; 2595 if ((err = snd_dbri_pcm(dbri)) < 0) 2596 goto _err; 2597 2598 if ((err = snd_dbri_mixer(dbri)) < 0) 2599 goto _err; 2600 2601 /* /proc file handling */ 2602 snd_dbri_proc(dbri); 2603 2604 if ((err = snd_card_register(card)) < 0) 2605 goto _err; 2606 2607 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n", 2608 dev, dbri->regs, 2609 dbri->irq, sdev->prom_name[9], dbri->mm.version); 2610 dev++; 2611 2612 return 0; 2613 2614 _err: 2615 snd_dbri_free(dbri); 2616 snd_card_free(card); 2617 return err; 2618} 2619 2620/* Probe for the dbri chip and then attach the driver. */ 2621static int __init dbri_init(void) 2622{ 2623 struct sbus_bus *sbus; 2624 struct sbus_dev *sdev; 2625 int found = 0; 2626 2627 /* Probe each SBUS for the DBRI chip(s). */ 2628 for_all_sbusdev(sdev, sbus) { 2629 /* 2630 * The version is coded in the last character 2631 */ 2632 if (!strncmp(sdev->prom_name, "SUNW,DBRI", 9)) { 2633 dprintk(D_GEN, "DBRI: Found %s in SBUS slot %d\n", 2634 sdev->prom_name, sdev->slot); 2635 2636 if (dbri_attach(sdev->prom_node, sdev) == 0) 2637 found++; 2638 } 2639 } 2640 2641 return (found > 0) ? 0 : -EIO; 2642} 2643 2644static void __exit dbri_exit(void) 2645{ 2646 struct snd_dbri *this = dbri_list; 2647 2648 while (this != NULL) { 2649 struct snd_dbri *next = this->next; 2650 struct snd_card *card = this->card; 2651 2652 snd_dbri_free(this); 2653 snd_card_free(card); 2654 this = next; 2655 } 2656 dbri_list = NULL; 2657} 2658 2659module_init(dbri_init); 2660module_exit(dbri_exit); 2661