| 167d5366c4dade2f90321c7f2ef9219cbd6fedcc |
|
04-Jun-2014 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: fix vi_sensor clocks on Tegra124
vi_sensor and vi_sensor2 have a wrong hw clkid on Tegra124. Fix this by
correcting the hw clkid for Tegra124 and creating the Tegra114 vi_sensor clock
from its own data. Tegra124 was also using the wrong internal clock id.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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| 5c992afcf8e4f91fac05d39b86c7f7922a50145c |
|
15-May-2014 |
Andrew Bresticker <abrestic@chromium.org> |
clk: tegra: Fix xusb_hs_src clock hierarchy
Currently the Tegra1x4 clock init code hard-codes the mux setting
for xusb_hs_src and treats it as a fixed-factor clock. It is,
however, a mux which can be parented by either xusb_ss_src/2 or
pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an
entry in periph_clks[] for the xusb_hs_src mux.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
|
| 9d61707b1f83324fc30918787cb6ef101997ecbd |
|
15-May-2014 |
Jim Lin <jilin@nvidia.com> |
clk: tegra: Fix xusb_fs_src mux
The parent-to-index mapping for xusb_fs_src is incorrect.
Fix it by adding a mux table.
Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
|
| a9952a76bc0c24b3c9d355c053e001b8a3b65dd3 |
|
19-Feb-2014 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: Fix vic03 mux index
The vic03 mux uses a linear mapping.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
|
| 20e7c323abac390deb35248705807bd844590048 |
|
27-Dec-2013 |
Andrew Bresticker <abrestic@chromium.org> |
clk: tegra: fix sdmmc clks on Tegra1x4
The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with
6 parents. Add support for tegra_clk_sdmmc*_8 and switch Tegra114
and Tegra124 to use these clocks instead.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
|
| 2edf3e035302776e4756e446baf3b6c7b94c3698 |
|
02-Dec-2013 |
Thierry Reding <thierry.reding@gmail.com> |
clk: tegra: Correct clock number for UARTE
UARTE has clock number 66. Number 65 is the right one for UARTD.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| 3b34d8214dce9bfeef9049de3fe1e8bfbbbb2709 |
|
14-Oct-2013 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra124: Add new peripheral clocks
Tegra124 introduces a number of new peripheral clocks. This patch adds those
to the common peripheral clock code.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
|
| b29f9e926442c35bd42ebd283aaed0de2c4f1477 |
|
18-Nov-2013 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: add TEGRA_PERIPH_NO_GATE
Tegra124 has a clock which consists of a mux and a fractional divider.
Add support for this.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| bc44275b8ea2df7c77658b08955ec545a37560ab |
|
18-Nov-2013 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: add locking to periph clks
Tegra124 has periph clocks which share the hw register. Hence locking is
required.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| 76ebc134d45d7e6e1dc29fdcef4e539c5bc76eb8 |
|
04-Sep-2013 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: move periph clocks to common file
Introduce a new file for peripheral clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure. Also PLLP and the PLLP_OUT
clocks will be initialized here.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
|