Lines Matching refs:val
13 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
15 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
18 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
23 #define bfin_write_SWRST(val) bfin_write16(SWRST,val)
25 #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
27 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
29 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
31 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
33 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
35 #define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
37 #define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
39 #define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
43 #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
45 #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
47 #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
51 #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
53 #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
55 #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
57 #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
59 #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
61 #define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
63 #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
67 #define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
69 #define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
73 #define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val)
75 #define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val)
77 #define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S,val)
79 #define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C,val)
81 #define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S,val)
83 #define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR,val)
85 #define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE,val)
87 #define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val)
89 #define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val)
91 #define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val)
93 #define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T,val)
95 #define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D,val)
97 #define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val)
101 #define BFIN_WRITE_FIO_FLAG(name, val) \
105 bfin_write16(FIO_FLAG_##name, val); \
109 #define bfin_write_FIO_FLAG_D(val) BFIN_WRITE_FIO_FLAG(D, val)
110 #define bfin_write_FIO_FLAG_C(val) BFIN_WRITE_FIO_FLAG(C, val)
111 #define bfin_write_FIO_FLAG_S(val) BFIN_WRITE_FIO_FLAG(S, val)
112 #define bfin_write_FIO_FLAG_T(val) BFIN_WRITE_FIO_FLAG(T, val)
130 #define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
131 #define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
132 #define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
133 #define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
142 #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
144 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
146 #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
148 #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
150 #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
152 #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
154 #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
156 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
158 #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
160 #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
162 #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
164 #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
166 #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
169 #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
171 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
173 #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
175 #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
177 #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
179 #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
181 #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
183 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
185 #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
187 #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
189 #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
191 #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
193 #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
196 #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
198 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
200 #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
202 #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
204 #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
206 #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
208 #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
210 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
212 #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
214 #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
216 #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
218 #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
220 #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
223 #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
225 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
227 #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
229 #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
231 #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
233 #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
235 #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
237 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
239 #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
241 #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
243 #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
245 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
247 #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
250 #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
252 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
254 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
256 #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
258 #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
260 #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
262 #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
264 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
266 #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
268 #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
270 #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
272 #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
274 #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
277 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
279 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
281 #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
283 #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
285 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
287 #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
289 #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
291 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
293 #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
295 #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
297 #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
299 #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
301 #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
304 #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
306 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
308 #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
310 #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
312 #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
314 #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
316 #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
318 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
320 #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
322 #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
324 #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
326 #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
328 #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
331 #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
333 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
335 #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
337 #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
339 #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
341 #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
343 #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
345 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
347 #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
349 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
351 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
353 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
355 #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
358 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
360 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
362 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
364 #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
366 #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
368 #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
370 #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
372 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
374 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
376 #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
378 #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
380 #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
382 #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
385 #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
387 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
389 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
391 #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
393 #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
395 #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
397 #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
399 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
401 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
403 #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
405 #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
407 #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
409 #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
412 #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
414 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
416 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
418 #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
420 #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
422 #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
424 #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
426 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
428 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
430 #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
432 #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
434 #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
436 #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
439 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
441 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
443 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
445 #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
447 #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
449 #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
451 #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
453 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
455 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
457 #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
459 #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
461 #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
463 #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
467 #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
469 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
471 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
475 #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
477 #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
479 #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
481 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
485 #define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
487 #define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
489 #define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
491 #define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
493 #define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
495 #define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
497 #define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
499 #define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
501 #define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
506 #define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
508 #define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
512 #define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
514 #define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
516 #define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
518 #define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
520 #define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
522 #define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
524 #define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
528 #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
530 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
532 #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
534 #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
537 #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
539 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
541 #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
543 #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
546 #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
548 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
550 #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
552 #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
555 #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
557 #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
559 #define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS,val)
563 #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
565 #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
567 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
569 #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
571 #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
573 #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
575 #define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
577 #define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
579 #define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
581 #define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
583 #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
585 #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
587 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
589 #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
591 #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
593 #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
595 #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
597 #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
599 #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
601 #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
603 #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
605 #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
607 #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
609 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
611 #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
613 #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
617 #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
619 #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
621 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
623 #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
625 #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
627 #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
629 #define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
631 #define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
633 #define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
635 #define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
637 #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
639 #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
641 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
643 #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
645 #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
647 #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
649 #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
651 #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
653 #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
655 #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
657 #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
659 #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
661 #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
663 #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
665 #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
667 #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
671 #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
673 #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
676 #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
678 #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
680 #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)