Cross Reference: /drivers/base/regmap/regcache.c

Lines Matching refs:cache
2  * Register cache access API
41 		dev_warn(map->dev, "No cache defaults, reading back from HW\n");
43 		/* Bypass the cache access till data read from HW*/
125 	map->cache = NULL;
146 		/* Some devices such as PMICs don't have cache defaults,
148 		 * crafting the cache defaults by hand.
159 		dev_dbg(map->dev, "Initializing %s cache\n",
187 		dev_dbg(map->dev, "Destroying %s cache\n",
194  * regcache_read: Fetch the value of a given register from the cache.
225  * regcache_write: Set the value of a given register in the cache.
284  * regcache_sync: Sync the register cache with the hardware.
306 	dev_dbg(map->dev, "Syncing %s cache\n",
351  * regcache_sync_region: Sync part  of the register cache with the hardware.
377 	dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
406  * regcache_drop_region: Discard part of the register cache
412  * Discard part of the register cache.
437  * regcache_cache_only: Put a register map into cache only mode
442  * When a register map is marked as cache only writes to the register
443  * map API will only update the register cache, they will not cause
459  * regcache_mark_dirty: Mark the register cache as dirty
463  * Mark the register cache as dirty, for example due to the device
464  * having been powered down for suspend.  If the cache is not marked
465  * as dirty then the cache sync will be suppressed.
476  * regcache_cache_bypass: Put a register map into cache bypass mode
481  * When a register map is marked with the cache bypass option, writes
483  * the cache directly.  This is useful when syncing the cache back to
511 		u8 *cache = base;
512 		cache[idx] = val;
516 		u16 *cache = base;
517 		cache[idx] = val;
521 		u32 *cache = base;
522 		cache[idx] = val;
544 		const u8 *cache = base;
545 		return cache[idx];
548 		const u16 *cache = base;
549 		return cache[idx];
552 		const u32 *cache = base;
553 		return cache[idx];