Lines Matching refs:div
22 * rate - rate is fixed. clk->rate = parent->rate / div * mult
35 do_div(rate, fix->div);
47 best_parent = (rate / fix->mult) * fix->div;
52 return (*prate / fix->div) * fix->mult;
70 unsigned int mult, unsigned int div)
84 fix->div = div;
111 u32 div, mult;
113 if (of_property_read_u32(node, "clock-div", &div)) {
114 pr_err("%s Fixed factor clock <%s> must have a clock-div property\n",
129 mult, div);