Cross Reference: /drivers/clk/clk-highbank.c

Lines Matching refs:reg
50 	void __iomem	*reg;
58 	u32 reg;
60 	reg = readl(hbclk->reg);
61 	reg &= ~HB_PLL_RESET;
62 	writel(reg, hbclk->reg);
64 	while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
66 	while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
75 	u32 reg;
77 	reg = readl(hbclk->reg);
78 	reg |= HB_PLL_RESET;
79 	writel(reg, hbclk->reg);
85 	u32 reg;
87 	reg = readl(hbclk->reg);
88 	reg |= HB_PLL_EXT_ENA;
89 	writel(reg, hbclk->reg);
97 	u32 reg;
99 	reg = readl(hbclk->reg);
100 	reg &= ~HB_PLL_EXT_ENA;
101 	writel(reg, hbclk->reg);
108 	unsigned long divf, divq, vco_freq, reg;
110 	reg = readl(hbclk->reg);
111 	if (reg & HB_PLL_EXT_BYPASS)
114 	divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT;
115 	divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;
161 	u32 reg;
165 	reg = readl(hbclk->reg);
166 	if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) {
168 		reg |= HB_PLL_EXT_BYPASS;
169 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
171 		writel(reg | HB_PLL_RESET, hbclk->reg);
172 		reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK);
173 		reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT);
174 		writel(reg | HB_PLL_RESET, hbclk->reg);
175 		writel(reg, hbclk->reg);
177 		while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
179 		while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
181 		reg |= HB_PLL_EXT_ENA;
182 		reg &= ~HB_PLL_EXT_BYPASS;
184 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
185 		reg &= ~HB_PLL_DIVQ_MASK;
186 		reg |= divq << HB_PLL_DIVQ_SHIFT;
187 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
189 	writel(reg, hbclk->reg);
208 	u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4;
220 	u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT;
235 	div = readl(hbclk->reg) & 0x1f;
264 	writel(div >> 1, hbclk->reg);
276 	u32 reg;
285 	rc = of_property_read_u32(node, "reg", &reg);
295 	hb_clk->reg = of_iomap(srnp, 0);
296 	BUG_ON(!hb_clk->reg);
297 	hb_clk->reg += reg;