Lines Matching refs:ret

81 	int ret;
83 ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_1);
84 if (ret < 0) {
86 ret);
90 return (ret & WM831X_FLL_ENA) != 0;
98 int ret;
100 ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1,
102 if (ret != 0)
103 dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);
107 return ret;
115 int ret;
117 ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1, WM831X_FLL_ENA, 0);
118 if (ret != 0)
119 dev_crit(wm831x->dev, "Failed to disable FLL: %d\n", ret);
128 int ret;
130 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
131 if (ret < 0) {
133 ret);
137 if (ret & WM831X_FLL_AUTO)
138 return wm831x_fll_auto_rates[ret & WM831X_FLL_AUTO_FREQ_MASK];
190 int ret;
193 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
194 if (ret < 0) {
196 ret);
200 if (ret & WM831X_FLL_AUTO)
203 ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_5);
204 if (ret < 0) {
206 ret);
210 switch (ret & WM831X_FLL_CLK_SRC_MASK) {
217 ret & WM831X_FLL_CLK_SRC_MASK);
245 int ret;
247 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
248 if (ret < 0) {
250 ret);
254 return (ret & WM831X_CLKOUT_ENA) != 0;
262 int ret;
264 ret = wm831x_reg_unlock(wm831x);
265 if (ret != 0) {
266 dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
267 return ret;
270 ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
272 if (ret != 0)
273 dev_crit(wm831x->dev, "Failed to enable CLKOUT: %d\n", ret);
277 return ret;
285 int ret;
287 ret = wm831x_reg_unlock(wm831x);
288 if (ret != 0) {
289 dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
293 ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
295 if (ret != 0)
296 dev_crit(wm831x->dev, "Failed to disable CLKOUT: %d\n", ret);
311 int ret;
313 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
314 if (ret < 0) {
316 ret);
320 if (ret & WM831X_CLKOUT_SRC)
357 int ret;
366 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
367 if (ret < 0) {
369 ret);
370 return ret;
372 clkdata->xtal_ena = ret & WM831X_XTAL_ENA;