Cross Reference: /drivers/clk/rockchip/clk-pll.c

Lines Matching refs:pll
52 			    struct rockchip_clk_pll *pll, unsigned long rate)
54 	const struct rockchip_pll_rate_table  *rate_table = pll->rate_table;
57 	for (i = 0; i < pll->rate_count; i++) {
68 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
69 	const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
73 	for (i = 0; i < pll->rate_count; i++) {
83  * Wait for the pll to reach the locked state.
87 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
94 		ret = regmap_read(grf, pll->lock_offset, &val);
96 			pr_err("%s: failed to read pll lock status: %d\n",
101 		if (val & BIT(pll->lock_shift))
106 	pr_err("%s: timeout waiting for pll to lock\n", __func__);
132 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
136 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
138 		pr_debug("%s: pll %s is bypassed\n", __func__,
143 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
146 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
160 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
164 	struct clk_mux *pll_mux = &pll->pll_mux;
165 	const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
180 	rate = rockchip_get_pll_settings(pll, drate);
182 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
198 	       pll->reg_base + RK3066_PLLCON(3));
200 	/* update pll values */
205 	       pll->reg_base + RK3066_PLLCON(0));
209 		       pll->reg_base + RK3066_PLLCON(1));
212 		       pll->reg_base + RK3066_PLLCON(2));
216 	       pll->reg_base + RK3066_PLLCON(3));
219 	/* wait for the pll to lock */
220 	ret = rockchip_pll_wait_lock(pll);
222 		pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
235 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
238 	       pll->reg_base + RK3066_PLLCON(3));
245 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
249 	       pll->reg_base + RK3066_PLLCON(3));
254 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
255 	u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
277  * Common registering of pll clocks
289 	struct rockchip_clk_pll *pll;
299 	/* name the actual pll */
302 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
303 	if (!pll)
321 		pll->rate_count = len;
322 		pll->rate_table = kmemdup(rate_table,
323 					pll->rate_count *
326 		WARN(!pll->rate_table,
333 		if (!pll->rate_table)
339 		pr_warn("%s: Unknown pll type for pll clk %s\n",
343 	pll->hw.init = &init;
344 	pll->type = pll_type;
345 	pll->reg_base = base + con_offset;
346 	pll->lock_offset = grf_lock_offset;
347 	pll->lock_shift = lock_shift;
348 	pll->lock = lock;
350 	pll_clk = clk_register(NULL, &pll->hw);
352 		pr_err("%s: failed to register pll clock %s : %ld\n",
358 	/* create the mux on top of the real pll */
359 	pll->pll_mux_ops = &clk_mux_ops;
360 	pll_mux = &pll->pll_mux;
362 	/* the actual muxing is xin24m, pll-output, xin32k */
369 	init.ops = pll->pll_mux_ops;
392 	kfree(pll);