Cross Reference: /drivers/clk/samsung/clk-pll.c

Lines Matching refs:pll
9  * This file contains the utility functions to register the pll clocks.
16 #include "clk-pll.h"
32 				struct samsung_clk_pll *pll, unsigned long rate)
34 	const struct samsung_pll_rate_table  *rate_table = pll->rate_table;
37 	for (i = 0; i < pll->rate_count; i++) {
48 	struct samsung_clk_pll *pll = to_clk_pll(hw);
49 	const struct samsung_pll_rate_table *rate_table = pll->rate_table;
53 	for (i = 0; i < pll->rate_count; i++) {
76 	struct samsung_clk_pll *pll = to_clk_pll(hw);
80 	pll_con = __raw_readl(pll->con_reg);
109 	struct samsung_clk_pll *pll = to_clk_pll(hw);
113 	pll_con = __raw_readl(pll->con_reg);
146 	struct samsung_clk_pll *pll = to_clk_pll(hw);
150 	pll_con = __raw_readl(pll->con_reg);
175 	struct samsung_clk_pll *pll = to_clk_pll(hw);
180 	rate = samsung_get_pll_settings(pll, drate);
182 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
187 	tmp = __raw_readl(pll->con_reg);
193 		__raw_writel(tmp, pll->con_reg);
200 			pll->lock_reg);
209 	__raw_writel(tmp, pll->con_reg);
214 		tmp = __raw_readl(pll->con_reg);
249 	struct samsung_clk_pll *pll = to_clk_pll(hw);
254 	pll_con0 = __raw_readl(pll->con_reg);
255 	pll_con1 = __raw_readl(pll->con_reg + 4);
284 	struct samsung_clk_pll *pll = to_clk_pll(hw);
288 	rate = samsung_get_pll_settings(pll, drate);
290 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
295 	pll_con0 = __raw_readl(pll->con_reg);
296 	pll_con1 = __raw_readl(pll->con_reg + 4);
302 		__raw_writel(pll_con0, pll->con_reg);
308 	__raw_writel(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);
317 	__raw_writel(pll_con0, pll->con_reg);
321 	__raw_writel(pll_con1, pll->con_reg + 4);
326 		tmp = __raw_readl(pll->con_reg);
363 	struct samsung_clk_pll *pll = to_clk_pll(hw);
367 	pll_con = __raw_readl(pll->con_reg);
372 	if (pll->type == pll_4508)
397 	struct samsung_clk_pll *pll = to_clk_pll(hw);
403 	rate = samsung_get_pll_settings(pll, drate);
405 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
410 	con0 = __raw_readl(pll->con_reg);
411 	con1 = __raw_readl(pll->con_reg + 0x4);
417 		__raw_writel(con0, pll->con_reg);
431 	con1 = __raw_readl(pll->con_reg + 0x4);
436 	switch (pll->type) {
438 		__raw_writel(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
441 		__raw_writel(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
448 	__raw_writel(con1, pll->con_reg + 0x4);
449 	__raw_writel(con0, pll->con_reg);
453 	while (!(__raw_readl(pll->con_reg) & PLL45XX_LOCKED)) {
508 	struct samsung_clk_pll *pll = to_clk_pll(hw);
512 	pll_con0 = __raw_readl(pll->con_reg);
513 	pll_con1 = __raw_readl(pll->con_reg + 4);
517 	kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
520 	shift = pll->type == pll_4600 ? 16 : 10;
544 	struct samsung_clk_pll *pll = to_clk_pll(hw);
550 	rate = samsung_get_pll_settings(pll, drate);
552 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
557 	con0 = __raw_readl(pll->con_reg);
558 	con1 = __raw_readl(pll->con_reg + 0x4);
564 		__raw_writel(con0, pll->con_reg);
586 	con1 = __raw_readl(pll->con_reg + 0x4);
595 	__raw_writel(lock, pll->lock_reg);
596 	__raw_writel(con0, pll->con_reg);
597 	__raw_writel(con1, pll->con_reg + 0x4);
601 	while (!(__raw_readl(pll->con_reg) & PLL46XX_LOCKED)) {
642 	struct samsung_clk_pll *pll = to_clk_pll(hw);
646 	pll_con = __raw_readl(pll->con_reg);
647 	if (pll->type == pll_6552_s3c2416) {
682 	struct samsung_clk_pll *pll = to_clk_pll(hw);
686 	pll_con0 = __raw_readl(pll->con_reg);
687 	pll_con1 = __raw_readl(pll->con_reg + 0x4);
720 	struct samsung_clk_pll *pll = to_clk_pll(hw);
724 	pll_con = __raw_readl(pll->con_reg);
738 	struct samsung_clk_pll *pll = to_clk_pll(hw);
742 	pll_con = __raw_readl(pll->con_reg);
756 	struct samsung_clk_pll *pll = to_clk_pll(hw);
761 	rate = samsung_get_pll_settings(pll, drate);
763 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
768 	tmp = __raw_readl(pll->con_reg);
777 	__raw_writel(tmp, pll->con_reg);
787 	struct samsung_clk_pll *pll = to_clk_pll(hw);
788 	u32 pll_en = __raw_readl(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);
796 	__raw_writel(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);
891 	struct samsung_clk_pll2550x *pll = to_clk_pll2550x(hw);
895 	pll_stat = __raw_readl(pll->reg_base + pll->offset * 3);
917 	struct samsung_clk_pll2550x *pll;
921 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
922 	if (!pll) {
923 		pr_err("%s: could not allocate pll clk %s\n", __func__, name);
933 	pll->hw.init = &init;
934 	pll->reg_base = reg_base;
935 	pll->offset = offset;
937 	clk = clk_register(NULL, &pll->hw);
939 		pr_err("%s: failed to register pll clock %s\n", __func__,
941 		kfree(pll);
969 	struct samsung_clk_pll *pll = to_clk_pll(hw);
973 	pll_con = __raw_readl(pll->con_reg);
997 	struct samsung_clk_pll *pll = to_clk_pll(hw);
1002 	rate = samsung_get_pll_settings(pll, drate);
1004 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
1009 	tmp = __raw_readl(pll->con_reg);
1015 		__raw_writel(tmp, pll->con_reg);
1021 	__raw_writel(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);
1030 	__raw_writel(tmp, pll->con_reg);
1035 		tmp = __raw_readl(pll->con_reg);
1074 	struct samsung_clk_pll *pll = to_clk_pll(hw);
1079 	pll_con0 = __raw_readl(pll->con_reg);
1080 	pll_con2 = __raw_readl(pll->con_reg + 8);
1096 	struct samsung_clk_pll *pll = to_clk_pll(hw);
1100 	rate = samsung_get_pll_settings(pll, drate);
1102 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
1107 	pll_con0 = __raw_readl(pll->con_reg);
1108 	pll_con2 = __raw_readl(pll->con_reg + 8);
1125 	__raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
1127 	__raw_writel(pll_con0, pll->con_reg);
1128 	__raw_writel(pll_con2, pll->con_reg + 8);
1131 		tmp = __raw_readl(pll->con_reg);
1151 	struct samsung_clk_pll *pll;
1156 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1157 	if (!pll) {
1158 		pr_err("%s: could not allocate pll clk %s\n",
1173 		pll->rate_count = len;
1174 		pll->rate_table = kmemdup(pll_clk->rate_table,
1175 					pll->rate_count *
1178 		WARN(!pll->rate_table,
1193 		if (!pll->rate_table)
1203 		if (!pll->rate_table)
1211 		if (!pll->rate_table)
1226 		if (!pll->rate_table)
1232 		if (!pll->rate_table)
1238 		if (!pll->rate_table)
1244 		if (!pll->rate_table)
1250 		if (!pll->rate_table)
1256 		if (!pll->rate_table)
1262 		pr_warn("%s: Unknown pll type for pll clk %s\n",
1266 	pll->hw.init = &init;
1267 	pll->type = pll_clk->type;
1268 	pll->lock_reg = base + pll_clk->lock_offset;
1269 	pll->con_reg = base + pll_clk->con_offset;
1271 	clk = clk_register(NULL, &pll->hw);
1273 		pr_err("%s: failed to register pll clock %s : %ld\n",
1275 		kfree(pll);