Lines Matching refs:val
149 unsigned long flags = 0, val;
157 val = readl_relaxed(pll->vco->cfg_reg);
158 val &= ~(PLL_DIV_P_MASK << PLL_DIV_P_SHIFT);
159 val |= (rtbl[i].p & PLL_DIV_P_MASK) << PLL_DIV_P_SHIFT;
160 writel_relaxed(val, pll->vco->cfg_reg);
197 unsigned int num = 2, den = 0, val, mode = 0;
204 val = readl_relaxed(vco->cfg_reg);
209 den = (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK;
214 num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK;
217 num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK;
235 unsigned long flags = 0, val;
244 val = readl_relaxed(vco->mode_reg);
245 val &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
246 val |= (rtbl[i].mode & PLL_MODE_MASK) << PLL_MODE_SHIFT;
247 writel_relaxed(val, vco->mode_reg);
249 val = readl_relaxed(vco->cfg_reg);
250 val &= ~(PLL_DIV_N_MASK << PLL_DIV_N_SHIFT);
251 val |= (rtbl[i].n & PLL_DIV_N_MASK) << PLL_DIV_N_SHIFT;
253 val &= ~(PLL_DITH_FDBK_M_MASK << PLL_DITH_FDBK_M_SHIFT);
255 val |= (rtbl[i].m & PLL_DITH_FDBK_M_MASK) <<
258 val |= (rtbl[i].m & PLL_NORM_FDBK_M_MASK) <<
261 writel_relaxed(val, vco->cfg_reg);