Lines Matching refs:cmd

267 	struct drv_cmd *cmd = _cmd;
270 switch (cmd->type) {
273 rdmsr(cmd->addr.msr.reg, cmd->val, h);
276 acpi_os_read_port((acpi_io_address)cmd->addr.io.port,
277 &cmd->val,
278 (u32)cmd->addr.io.bit_width);
288 struct drv_cmd *cmd = _cmd;
291 switch (cmd->type) {
293 rdmsr(cmd->addr.msr.reg, lo, hi);
294 lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE);
295 wrmsr(cmd->addr.msr.reg, lo, hi);
298 wrmsr(cmd->addr.msr.reg, cmd->val, 0);
301 acpi_os_write_port((acpi_io_address)cmd->addr.io.port,
302 cmd->val,
303 (u32)cmd->addr.io.bit_width);
310 static void drv_read(struct drv_cmd *cmd)
313 cmd->val = 0;
315 err = smp_call_function_any(cmd->mask, do_drv_read, cmd, 1);
319 static void drv_write(struct drv_cmd *cmd)
324 if (cpumask_test_cpu(this_cpu, cmd->mask))
325 do_drv_write(cmd);
326 smp_call_function_many(cmd->mask, do_drv_write, cmd, 1);
333 struct drv_cmd cmd;
340 cmd.type = SYSTEM_INTEL_MSR_CAPABLE;
341 cmd.addr.msr.reg = MSR_IA32_PERF_CTL;
344 cmd.type = SYSTEM_AMD_MSR_CAPABLE;
345 cmd.addr.msr.reg = MSR_AMD_PERF_CTL;
348 cmd.type = SYSTEM_IO_CAPABLE;
350 cmd.addr.io.port = perf->control_register.address;
351 cmd.addr.io.bit_width = perf->control_register.bit_width;
357 cmd.mask = mask;
358 drv_read(&cmd);
360 pr_debug("get_cur_val = %u\n", cmd.val);
362 return cmd.val;
413 struct drv_cmd cmd;
438 cmd.type = SYSTEM_INTEL_MSR_CAPABLE;
439 cmd.addr.msr.reg = MSR_IA32_PERF_CTL;
440 cmd.val = (u32) perf->states[next_perf_state].control;
443 cmd.type = SYSTEM_AMD_MSR_CAPABLE;
444 cmd.addr.msr.reg = MSR_AMD_PERF_CTL;
445 cmd.val = (u32) perf->states[next_perf_state].control;
448 cmd.type = SYSTEM_IO_CAPABLE;
449 cmd.addr.io.port = perf->control_register.address;
450 cmd.addr.io.bit_width = perf->control_register.bit_width;
451 cmd.val = (u32) perf->states[next_perf_state].control;
460 cmd.mask = policy->cpus;
462 cmd.mask = cpumask_of(policy->cpu);
464 drv_write(&cmd);
467 if (!check_freqs(cmd.mask, data->freq_table[index].frequency,