Lines Matching defs:TXX9_DMA_REG32
63 #define TXX9_DMA_REG32(name) u32 __pad_##name; u32 name
65 #define TXX9_DMA_REG32(name) u32 name; u32 __pad_##name
71 TXX9_DMA_REG32(CHAR); /* Chain Address Register */
77 TXX9_DMA_REG32(CNTR); /* Count Register */
78 TXX9_DMA_REG32(SAIR); /* Source Address Increment Register */
79 TXX9_DMA_REG32(DAIR); /* Destination Address Increment Register */
80 TXX9_DMA_REG32(CCR); /* Channel Control Register */
81 TXX9_DMA_REG32(CSR); /* Channel Status Register */
99 TXX9_DMA_REG32(MCR); /* Master Control Register */
205 TXX9_DMA_REG32(CHAR);
211 TXX9_DMA_REG32(CNTR);