Lines Matching refs:mask
178 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_ATTACH_MASK, },
179 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_DETACH_MASK, },
180 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_KP_MASK, },
181 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_LKP_MASK, },
182 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_LKR_MASK, },
183 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_OVP_EVENT_MASK, },
184 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_OCP_EVENT_MASK, },
185 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_OVP_OCP_DIS_MASK, },
188 { .reg_offset = 1, .mask = SM5502_IRQ_INT2_VBUS_DET_MASK,},
189 { .reg_offset = 1, .mask = SM5502_IRQ_INT2_REV_ACCE_MASK, },
190 { .reg_offset = 1, .mask = SM5502_IRQ_INT2_ADC_CHG_MASK, },
191 { .reg_offset = 1, .mask = SM5502_IRQ_INT2_STUCK_KEY_MASK, },
192 { .reg_offset = 1, .mask = SM5502_IRQ_INT2_STUCK_KEY_RCV_MASK, },
193 { .reg_offset = 1, .mask = SM5502_IRQ_INT2_MHL_MASK, },