Lines Matching refs:bank
78 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
84 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
85 #define GPIO_BIT(bank, gpio) (BIT(GPIO_INDEX(bank, gpio)))
88 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
91 static int omap_irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
93 return bank->chip.base + gpio_irq;
102 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
105 void __iomem *reg = bank->base;
108 reg += bank->regs->direction;
115 bank->context.oe = l;
120 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, int gpio,
123 void __iomem *reg = bank->base;
124 u32 l = GPIO_BIT(bank, gpio);
127 reg += bank->regs->set_dataout;
128 bank->context.dataout |= l;
130 reg += bank->regs->clr_dataout;
131 bank->context.dataout &= ~l;
138 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, int gpio,
141 void __iomem *reg = bank->base + bank->regs->dataout;
142 u32 gpio_bit = GPIO_BIT(bank, gpio);
151 bank->context.dataout = l;
154 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
156 void __iomem *reg = bank->base + bank->regs->datain;
161 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
163 void __iomem *reg = bank->base + bank->regs->dataout;
180 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
182 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
183 clk_prepare_enable(bank->dbck);
184 bank->dbck_enabled = true;
186 writel_relaxed(bank->dbck_enable_mask,
187 bank->base + bank->regs->debounce_en);
191 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
193 if (bank->dbck_enable_mask && bank->dbck_enabled) {
199 writel_relaxed(0, bank->base + bank->regs->debounce_en);
201 clk_disable_unprepare(bank->dbck);
202 bank->dbck_enabled = false;
208 * @bank: the gpio bank we're acting upon
215 static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
222 if (!bank->dbck_flag)
232 l = GPIO_BIT(bank, gpio);
234 clk_prepare_enable(bank->dbck);
235 reg = bank->base + bank->regs->debounce;
238 reg = bank->base + bank->regs->debounce_en;
245 bank->dbck_enable_mask = val;
248 clk_disable_unprepare(bank->dbck);
257 omap_gpio_dbck_enable(bank);
258 if (bank->dbck_enable_mask) {
259 bank->context.debounce = debounce;
260 bank->context.debounce_en = val;
266 * @bank: the gpio bank we're acting upon
270 * this is the only gpio in this bank using debounce, then clear the debounce
272 * if this is the only gpio in the bank using debounce.
274 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio)
276 u32 gpio_bit = GPIO_BIT(bank, gpio);
278 if (!bank->dbck_flag)
281 if (!(bank->dbck_enable_mask & gpio_bit))
284 bank->dbck_enable_mask &= ~gpio_bit;
285 bank->context.debounce_en &= ~gpio_bit;
286 writel_relaxed(bank->context.debounce_en,
287 bank->base + bank->regs->debounce_en);
289 if (!bank->dbck_enable_mask) {
290 bank->context.debounce = 0;
291 writel_relaxed(bank->context.debounce, bank->base +
292 bank->regs->debounce);
293 clk_disable_unprepare(bank->dbck);
294 bank->dbck_enabled = false;
298 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
301 void __iomem *base = bank->base;
304 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
306 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
308 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
310 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
313 bank->context.leveldetect0 =
314 readl_relaxed(bank->base + bank->regs->leveldetect0);
315 bank->context.leveldetect1 =
316 readl_relaxed(bank->base + bank->regs->leveldetect1);
317 bank->context.risingdetect =
318 readl_relaxed(bank->base + bank->regs->risingdetect);
319 bank->context.fallingdetect =
320 readl_relaxed(bank->base + bank->regs->fallingdetect);
322 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
323 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
324 bank->context.wake_en =
325 readl_relaxed(bank->base + bank->regs->wkup_en);
329 if (!bank->regs->irqctrl) {
331 if (bank->non_wakeup_gpios) {
332 if (!(bank->non_wakeup_gpios & gpio_bit))
343 bank->enabled_non_wakeup_gpios |= gpio_bit;
345 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
349 bank->level_mask =
350 readl_relaxed(bank->base + bank->regs->leveldetect0) |
351 readl_relaxed(bank->base + bank->regs->leveldetect1);
359 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
361 void __iomem *reg = bank->base;
364 if (!bank->regs->irqctrl)
367 reg += bank->regs->irqctrl;
378 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
381 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
384 void __iomem *reg = bank->base;
385 void __iomem *base = bank->base;
388 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
389 omap_set_gpio_trigger(bank, gpio, trigger);
390 } else if (bank->regs->irqctrl) {
391 reg += bank->regs->irqctrl;
395 bank->toggle_mask |= BIT(gpio);
404 } else if (bank->regs->edgectrl1) {
406 reg += bank->regs->edgectrl2;
408 reg += bank->regs->edgectrl1;
419 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
420 bank->context.wake_en =
421 readl_relaxed(bank->base + bank->regs->wkup_en);
427 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
429 if (bank->regs->pinctrl) {
430 void __iomem *reg = bank->base + bank->regs->pinctrl;
436 if (bank->regs->ctrl && !BANK_USED(bank)) {
437 void __iomem *reg = bank->base + bank->regs->ctrl;
444 bank->context.ctrl = ctrl;
448 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
450 void __iomem *base = bank->base;
452 if (bank->regs->wkup_en &&
453 !LINE_USED(bank->mod_usage, offset) &&
454 !LINE_USED(bank->irq_usage, offset)) {
456 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
457 bank->context.wake_en =
458 readl_relaxed(bank->base + bank->regs->wkup_en);
461 if (bank->regs->ctrl && !BANK_USED(bank)) {
462 void __iomem *reg = bank->base + bank->regs->ctrl;
469 bank->context.ctrl = ctrl;
473 static int omap_gpio_is_input(struct gpio_bank *bank, int mask)
475 void __iomem *reg = bank->base + bank->regs->direction;
482 struct gpio_bank *bank = omap_irq_data_get_bank(d);
488 if (!BANK_USED(bank))
489 pm_runtime_get_sync(bank->dev);
497 gpio = omap_irq_to_gpio(bank, d->hwirq);
502 if (!bank->regs->leveldetect0 &&
506 spin_lock_irqsave(&bank->lock, flags);
507 offset = GPIO_INDEX(bank, gpio);
508 retval = omap_set_gpio_triggering(bank, offset, type);
509 if (!LINE_USED(bank->mod_usage, offset)) {
510 omap_enable_gpio_module(bank, offset);
511 omap_set_gpio_direction(bank, offset, 1);
512 } else if (!omap_gpio_is_input(bank, BIT(offset))) {
513 spin_unlock_irqrestore(&bank->lock, flags);
517 bank->irq_usage |= BIT(GPIO_INDEX(bank, gpio));
518 spin_unlock_irqrestore(&bank->lock, flags);
528 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
530 void __iomem *reg = bank->base;
532 reg += bank->regs->irqstatus;
536 if (bank->regs->irqstatus2) {
537 reg = bank->base + bank->regs->irqstatus2;
545 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
547 omap_clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
550 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
552 void __iomem *reg = bank->base;
554 u32 mask = (BIT(bank->width)) - 1;
556 reg += bank->regs->irqenable;
558 if (bank->regs->irqenable_inv)
564 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
566 void __iomem *reg = bank->base;
569 if (bank->regs->set_irqenable) {
570 reg += bank->regs->set_irqenable;
572 bank->context.irqenable1 |= gpio_mask;
574 reg += bank->regs->irqenable;
576 if (bank->regs->irqenable_inv)
580 bank->context.irqenable1 = l;
586 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
588 void __iomem *reg = bank->base;
591 if (bank->regs->clr_irqenable) {
592 reg += bank->regs->clr_irqenable;
594 bank->context.irqenable1 &= ~gpio_mask;
596 reg += bank->regs->irqenable;
598 if (bank->regs->irqenable_inv)
602 bank->context.irqenable1 = l;
608 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, int gpio,
612 omap_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
614 omap_disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
625 static int omap_set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
627 u32 gpio_bit = GPIO_BIT(bank, gpio);
630 if (bank->non_wakeup_gpios & gpio_bit) {
631 dev_err(bank->dev,
636 spin_lock_irqsave(&bank->lock, flags);
638 bank->context.wake_en |= gpio_bit;
640 bank->context.wake_en &= ~gpio_bit;
642 writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
643 spin_unlock_irqrestore(&bank->lock, flags);
648 static void omap_reset_gpio(struct gpio_bank *bank, int gpio)
650 omap_set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
651 omap_set_gpio_irqenable(bank, gpio, 0);
652 omap_clear_gpio_irqstatus(bank, gpio);
653 omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
654 omap_clear_gpio_debounce(bank, gpio);
660 struct gpio_bank *bank = omap_irq_data_get_bank(d);
661 unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq);
663 return omap_set_gpio_wakeup(bank, gpio, enable);
668 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
672 * If this is the first gpio_request for the bank,
673 * enable the bank module.
675 if (!BANK_USED(bank))
676 pm_runtime_get_sync(bank->dev);
678 spin_lock_irqsave(&bank->lock, flags);
683 if (!LINE_USED(bank->irq_usage, offset)) {
684 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
685 omap_enable_gpio_module(bank, offset);
687 bank->mod_usage |= BIT(offset);
688 spin_unlock_irqrestore(&bank->lock, flags);
695 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
698 spin_lock_irqsave(&bank->lock, flags);
699 bank->mod_usage &= ~(BIT(offset));
700 omap_disable_gpio_module(bank, offset);
701 omap_reset_gpio(bank, bank->chip.base + offset);
702 spin_unlock_irqrestore(&bank->lock, flags);
705 * If this is the last gpio to be freed in the bank,
706 * disable the bank module.
708 if (!BANK_USED(bank))
709 pm_runtime_put(bank->dev);
713 * We need to unmask the GPIO bank interrupt as soon as possible to
714 * avoid missing GPIO interrupts for other lines in the bank.
716 * in the bank to avoid missing nested interrupts for a GPIO line.
717 * If we wait to unmask individual GPIO lines in the bank after the
726 struct gpio_bank *bank;
733 bank = container_of(chip, struct gpio_bank, chip);
734 isr_reg = bank->base + bank->regs->irqstatus;
735 pm_runtime_get_sync(bank->dev);
744 enabled = omap_get_gpio_irqbank_mask(bank);
747 if (bank->level_mask)
748 level_mask = bank->level_mask & enabled;
753 omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
754 omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
755 omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
758 configured, we could unmask GPIO bank interrupt immediately */
776 * This will be indicated in the bank toggle_mask.
778 if (bank->toggle_mask & (BIT(bit)))
779 omap_toggle_gpio_edge_triggering(bank, bit);
781 generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
785 /* if bank has any level sensitive GPIO pin interrupt
786 configured, we must unmask the bank interrupt only after
787 handler(s) are executed in order to avoid spurious bank
792 pm_runtime_put(bank->dev);
797 struct gpio_bank *bank = omap_irq_data_get_bank(d);
798 unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq);
800 unsigned offset = GPIO_INDEX(bank, gpio);
802 spin_lock_irqsave(&bank->lock, flags);
803 gpio_unlock_as_irq(&bank->chip, offset);
804 bank->irq_usage &= ~(BIT(offset));
805 omap_disable_gpio_module(bank, offset);
806 omap_reset_gpio(bank, gpio);
807 spin_unlock_irqrestore(&bank->lock, flags);
810 * If this is the last IRQ to be freed in the bank,
811 * disable the bank module.
813 if (!BANK_USED(bank))
814 pm_runtime_put(bank->dev);
819 struct gpio_bank *bank = omap_irq_data_get_bank(d);
820 unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq);
822 omap_clear_gpio_irqstatus(bank, gpio);
827 struct gpio_bank *bank = omap_irq_data_get_bank(d);
828 unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq);
831 spin_lock_irqsave(&bank->lock, flags);
832 omap_set_gpio_irqenable(bank, gpio, 0);
833 omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
834 spin_unlock_irqrestore(&bank->lock, flags);
839 struct gpio_bank *bank = omap_irq_data_get_bank(d);
840 unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq);
841 unsigned int irq_mask = GPIO_BIT(bank, gpio);
845 spin_lock_irqsave(&bank->lock, flags);
847 omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
851 if (bank->level_mask & irq_mask) {
852 omap_set_gpio_irqenable(bank, gpio, 0);
853 omap_clear_gpio_irqstatus(bank, gpio);
856 omap_set_gpio_irqenable(bank, gpio, 1);
857 spin_unlock_irqrestore(&bank->lock, flags);
865 struct gpio_bank *bank = platform_get_drvdata(pdev);
866 void __iomem *mask_reg = bank->base +
867 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
870 spin_lock_irqsave(&bank->lock, flags);
871 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
872 spin_unlock_irqrestore(&bank->lock, flags);
880 struct gpio_bank *bank = platform_get_drvdata(pdev);
881 void __iomem *mask_reg = bank->base +
882 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
885 spin_lock_irqsave(&bank->lock, flags);
886 writel_relaxed(bank->context.wake_en, mask_reg);
887 spin_unlock_irqrestore(&bank->lock, flags);
914 static inline void omap_mpuio_init(struct gpio_bank *bank)
916 platform_set_drvdata(&omap_mpuio_device, bank);
926 struct gpio_bank *bank;
931 bank = container_of(chip, struct gpio_bank, chip);
932 reg = bank->base + bank->regs->direction;
933 spin_lock_irqsave(&bank->lock, flags);
935 spin_unlock_irqrestore(&bank->lock, flags);
941 struct gpio_bank *bank;
944 bank = container_of(chip, struct gpio_bank, chip);
945 spin_lock_irqsave(&bank->lock, flags);
946 omap_set_gpio_direction(bank, offset, 1);
947 spin_unlock_irqrestore(&bank->lock, flags);
953 struct gpio_bank *bank;
956 bank = container_of(chip, struct gpio_bank, chip);
959 if (omap_gpio_is_input(bank, mask))
960 return omap_get_gpio_datain(bank, offset);
962 return omap_get_gpio_dataout(bank, offset);
967 struct gpio_bank *bank;
970 bank = container_of(chip, struct gpio_bank, chip);
971 spin_lock_irqsave(&bank->lock, flags);
972 bank->set_dataout(bank, offset, value);
973 omap_set_gpio_direction(bank, offset, 0);
974 spin_unlock_irqrestore(&bank->lock, flags);
981 struct gpio_bank *bank;
984 bank = container_of(chip, struct gpio_bank, chip);
986 spin_lock_irqsave(&bank->lock, flags);
987 omap2_set_gpio_debounce(bank, offset, debounce);
988 spin_unlock_irqrestore(&bank->lock, flags);
995 struct gpio_bank *bank;
998 bank = container_of(chip, struct gpio_bank, chip);
999 spin_lock_irqsave(&bank->lock, flags);
1000 bank->set_dataout(bank, offset, value);
1001 spin_unlock_irqrestore(&bank->lock, flags);
1006 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1011 if (called || bank->regs->revision == USHRT_MAX)
1014 rev = readw_relaxed(bank->base + bank->regs->revision);
1021 static void omap_gpio_mod_init(struct gpio_bank *bank)
1023 void __iomem *base = bank->base;
1026 if (bank->width == 16)
1029 if (bank->is_mpuio) {
1030 writel_relaxed(l, bank->base + bank->regs->irqenable);
1034 omap_gpio_rmw(base, bank->regs->irqenable, l,
1035 bank->regs->irqenable_inv);
1036 omap_gpio_rmw(base, bank->regs->irqstatus, l,
1037 !bank->regs->irqenable_inv);
1038 if (bank->regs->debounce_en)
1039 writel_relaxed(0, base + bank->regs->debounce_en);
1042 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1044 if (bank->regs->ctrl)
1045 writel_relaxed(0, base + bank->regs->ctrl);
1047 bank->dbck = clk_get(bank->dev, "dbclk");
1048 if (IS_ERR(bank->dbck))
1049 dev_err(bank->dev, "Could not get gpio dbck\n");
1053 omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1059 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1062 dev_err(bank->dev, "Memory alloc failed for gc\n");
1073 if (bank->regs->wkup_en)
1076 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1081 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1092 bank->chip.request = omap_gpio_request;
1093 bank->chip.free = omap_gpio_free;
1094 bank->chip.get_direction = omap_gpio_get_direction;
1095 bank->chip.direction_input = omap_gpio_input;
1096 bank->chip.get = omap_gpio_get;
1097 bank->chip.direction_output = omap_gpio_output;
1098 bank->chip.set_debounce = omap_gpio_debounce;
1099 bank->chip.set = omap_gpio_set;
1100 if (bank->is_mpuio) {
1101 bank->chip.label = "mpuio";
1102 if (bank->regs->wkup_en)
1103 bank->chip.dev = &omap_mpuio_device.dev;
1104 bank->chip.base = OMAP_MPUIO(0);
1106 bank->chip.label = "gpio";
1107 bank->chip.base = gpio;
1108 gpio += bank->width;
1110 bank->chip.ngpio = bank->width;
1112 ret = gpiochip_add(&bank->chip);
1114 dev_err(bank->dev, "Could not register gpio chip %d\n", ret);
1123 irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1125 dev_err(bank->dev, "Couldn't allocate IRQ numbers\n");
1130 ret = gpiochip_irqchip_add(&bank->chip, irqc,
1135 dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret);
1136 gpiochip_remove(&bank->chip);
1140 gpiochip_set_chained_irqchip(&bank->chip, irqc,
1141 bank->irq, omap_gpio_irq_handler);
1143 for (j = 0; j < bank->width; j++) {
1144 int irq = irq_find_mapping(bank->chip.irqdomain, j);
1145 if (bank->is_mpuio) {
1146 omap_mpuio_alloc_gc(bank, irq, bank->width);
1164 struct gpio_bank *bank;
1174 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1175 if (!bank) {
1198 bank->irq = res->start;
1199 bank->dev = dev;
1200 bank->chip.dev = dev;
1201 bank->dbck_flag = pdata->dbck_flag;
1202 bank->stride = pdata->bank_stride;
1203 bank->width = pdata->bank_width;
1204 bank->is_mpuio = pdata->is_mpuio;
1205 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1206 bank->regs = pdata->regs;
1208 bank->chip.of_node = of_node_get(node);
1212 bank->loses_context = true;
1214 bank->loses_context = pdata->loses_context;
1216 if (bank->loses_context)
1217 bank->get_context_loss_count =
1221 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1222 bank->set_dataout = omap_set_gpio_dataout_reg;
1224 bank->set_dataout = omap_set_gpio_dataout_mask;
1226 spin_lock_init(&bank->lock);
1230 bank->base = devm_ioremap_resource(dev, res);
1231 if (IS_ERR(bank->base)) {
1232 irq_domain_remove(bank->chip.irqdomain);
1233 return PTR_ERR(bank->base);
1236 platform_set_drvdata(pdev, bank);
1238 pm_runtime_enable(bank->dev);
1239 pm_runtime_irq_safe(bank->dev);
1240 pm_runtime_get_sync(bank->dev);
1242 if (bank->is_mpuio)
1243 omap_mpuio_init(bank);
1245 omap_gpio_mod_init(bank);
1247 ret = omap_gpio_chip_init(bank, irqc);
1251 omap_gpio_show_rev(bank);
1253 pm_runtime_put(bank->dev);
1255 list_add_tail(&bank->node, &omap_gpio_list);
1263 static void omap_gpio_restore_context(struct gpio_bank *bank);
1268 struct gpio_bank *bank = platform_get_drvdata(pdev);
1273 spin_lock_irqsave(&bank->lock, flags);
1284 * by writing back the values saved in bank->context.
1286 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1288 writel_relaxed(wake_low | bank->context.fallingdetect,
1289 bank->base + bank->regs->fallingdetect);
1290 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1292 writel_relaxed(wake_hi | bank->context.risingdetect,
1293 bank->base + bank->regs->risingdetect);
1295 if (!bank->enabled_non_wakeup_gpios)
1298 if (bank->power_mode != OFF_MODE) {
1299 bank->power_mode = 0;
1307 bank->saved_datain = readl_relaxed(bank->base +
1308 bank->regs->datain);
1309 l1 = bank->context.fallingdetect;
1310 l2 = bank->context.risingdetect;
1312 l1 &= ~bank->enabled_non_wakeup_gpios;
1313 l2 &= ~bank->enabled_non_wakeup_gpios;
1315 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1316 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1318 bank->workaround_enabled = true;
1321 if (bank->get_context_loss_count)
1322 bank->context_loss_count =
1323 bank->get_context_loss_count(bank->dev);
1325 omap_gpio_dbck_disable(bank);
1326 spin_unlock_irqrestore(&bank->lock, flags);
1336 struct gpio_bank *bank = platform_get_drvdata(pdev);
1341 spin_lock_irqsave(&bank->lock, flags);
1348 if (bank->loses_context && !bank->context_valid) {
1349 omap_gpio_init_context(bank);
1351 if (bank->get_context_loss_count)
1352 bank->context_loss_count =
1353 bank->get_context_loss_count(bank->dev);
1356 omap_gpio_dbck_enable(bank);
1364 writel_relaxed(bank->context.fallingdetect,
1365 bank->base + bank->regs->fallingdetect);
1366 writel_relaxed(bank->context.risingdetect,
1367 bank->base + bank->regs->risingdetect);
1369 if (bank->loses_context) {
1370 if (!bank->get_context_loss_count) {
1371 omap_gpio_restore_context(bank);
1373 c = bank->get_context_loss_count(bank->dev);
1374 if (c != bank->context_loss_count) {
1375 omap_gpio_restore_context(bank);
1377 spin_unlock_irqrestore(&bank->lock, flags);
1383 if (!bank->workaround_enabled) {
1384 spin_unlock_irqrestore(&bank->lock, flags);
1388 l = readl_relaxed(bank->base + bank->regs->datain);
1396 l ^= bank->saved_datain;
1397 l &= bank->enabled_non_wakeup_gpios;
1403 gen0 = l & bank->context.fallingdetect;
1404 gen0 &= bank->saved_datain;
1406 gen1 = l & bank->context.risingdetect;
1407 gen1 &= ~(bank->saved_datain);
1410 gen = l & (~(bank->context.fallingdetect) &
1411 ~(bank->context.risingdetect));
1418 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1419 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1421 if (!bank->regs->irqstatus_raw0) {
1422 writel_relaxed(old0 | gen, bank->base +
1423 bank->regs->leveldetect0);
1424 writel_relaxed(old1 | gen, bank->base +
1425 bank->regs->leveldetect1);
1428 if (bank->regs->irqstatus_raw0) {
1429 writel_relaxed(old0 | l, bank->base +
1430 bank->regs->leveldetect0);
1431 writel_relaxed(old1 | l, bank->base +
1432 bank->regs->leveldetect1);
1434 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1435 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1438 bank->workaround_enabled = false;
1439 spin_unlock_irqrestore(&bank->lock, flags);
1447 struct gpio_bank *bank;
1449 list_for_each_entry(bank, &omap_gpio_list, node) {
1450 if (!BANK_USED(bank) || !bank->loses_context)
1453 bank->power_mode = pwr_mode;
1455 pm_runtime_put_sync_suspend(bank->dev);
1461 struct gpio_bank *bank;
1463 list_for_each_entry(bank, &omap_gpio_list, node) {
1464 if (!BANK_USED(bank) || !bank->loses_context)
1467 pm_runtime_get_sync(bank->dev);
1495 static void omap_gpio_restore_context(struct gpio_bank *bank)
1497 writel_relaxed(bank->context.wake_en,
1498 bank->base + bank->regs->wkup_en);
1499 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1500 writel_relaxed(bank->context.leveldetect0,
1501 bank->base + bank->regs->leveldetect0);
1502 writel_relaxed(bank->context.leveldetect1,
1503 bank->base + bank->regs->leveldetect1);
1504 writel_relaxed(bank->context.risingdetect,
1505 bank->base + bank->regs->risingdetect);
1506 writel_relaxed(bank->context.fallingdetect,
1507 bank->base + bank->regs->fallingdetect);
1508 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1509 writel_relaxed(bank->context.dataout,
1510 bank->base + bank->regs->set_dataout);
1512 writel_relaxed(bank->context.dataout,
1513 bank->base + bank->regs->dataout);
1514 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1516 if (bank->dbck_enable_mask) {
1517 writel_relaxed(bank->context.debounce, bank->base +
1518 bank->regs->debounce);
1519 writel_relaxed(bank->context.debounce_en,
1520 bank->base + bank->regs->debounce_en);
1523 writel_relaxed(bank->context.irqenable1,
1524 bank->base + bank->regs->irqenable);
1525 writel_relaxed(bank->context.irqenable2,
1526 bank->base + bank->regs->irqenable2);