Cross Reference: /drivers/gpu/drm/exynos/exynos_drm

Lines Matching refs:reg_base
278 	void __iomem *reg_base;
353 	writel(DSIM_SWRST, dsi->reg_base + DSIM_SWRST_REG);
440 	writel(500, dsi->reg_base + driver_data->plltmr_reg);
462 	writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
470 		reg = readl(dsi->reg_base + DSIM_STATUS_REG);
500 	reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
510 	writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
525 	writel(reg, dsi->reg_base + DSIM_PHYCTRL_REG);
533 	writel(reg, dsi->reg_base + DSIM_PHYTIMING_REG);
552 	writel(reg, dsi->reg_base + DSIM_PHYTIMING1_REG);
565 	writel(reg, dsi->reg_base + DSIM_PHYTIMING2_REG);
572 	reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
575 	writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
577 	reg = readl(dsi->reg_base + DSIM_PLLCTRL_REG);
579 	writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
590 	reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
592 	writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
597 	writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
657 	writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
660 	writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
664 	writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
677 		writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
688 		reg = readl(dsi->reg_base + DSIM_STATUS_REG);
694 	reg = readl(dsi->reg_base + DSIM_ESCMODE_REG);
697 	writel(reg, dsi->reg_base + DSIM_ESCMODE_REG);
700 	writel(reg, dsi->reg_base + DSIM_TIMEOUT_REG);
714 		writel(reg, dsi->reg_base + DSIM_MVPORCH_REG);
718 		writel(reg, dsi->reg_base + DSIM_MHPORCH_REG);
722 		writel(reg, dsi->reg_base + DSIM_MSYNC_REG);
726 	writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
735 	reg = readl(dsi->reg_base + DSIM_MDRESOL_REG);
740 	writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
748 		u32 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
762 	u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
769 	writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
774 	u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
777 	writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
801 		writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
816 		writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
839 	writel(reg, dsi->reg_base + DSIM_PKTHDR_REG);
855 		reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
894 		reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
904 		reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
923 		reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
1079 	status = readl(dsi->reg_base + DSIM_INTSRC_REG);
1086 	writel(status, dsi->reg_base + DSIM_INTSRC_REG);
1090 		writel(mask, dsi->reg_base + DSIM_INTMSK_REG);
1733 	dsi->reg_base = devm_ioremap_resource(&pdev->dev, res);
1734 	if (IS_ERR(dsi->reg_base)) {
1736 		ret = PTR_ERR(dsi->reg_base);