Lines Matching refs:lane_count
70 uint8_t lane_count;
706 int lane_count, clock;
719 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
721 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count);
725 intel_dp->lane_count = lane_count;
729 intel_dp->link_bw, intel_dp->lane_count,
737 intel_dp->lane_count = max_lane_count;
742 intel_dp->link_bw, intel_dp->lane_count,
799 int lane_count = 4, bpp = 24;
816 lane_count = intel_dp->lane_count;
819 lane_count = intel_dp->lane_count;
830 cdv_intel_dp_compute_m_n(bpp, lane_count,
863 switch (intel_dp->lane_count) {
879 intel_dp->link_configuration[1] = intel_dp->lane_count;
1118 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1152 cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1157 for (lane = 0; lane < lane_count; lane++) {
1181 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1227 intel_dp->lane_count);
1229 if (ret != intel_dp->lane_count) {
1231 intel_dp->train_set[0], intel_dp->lane_count);
1363 if (cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1370 for (i = 0; i < intel_dp->lane_count; i++)
1373 if (i == intel_dp->lane_count)
1448 if (!cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {