Lines Matching defs:sarea_priv

353 	dev_priv->sarea_priv = (drm_i810_sarea_t *)
559 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
560 unsigned int dirty = sarea_priv->dirty;
565 i810EmitDestVerified(dev, sarea_priv->BufferState);
566 sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
570 i810EmitContextVerified(dev, sarea_priv->ContextState);
571 sarea_priv->dirty &= ~I810_UPLOAD_CTX;
575 i810EmitTexVerified(dev, sarea_priv->TexState[0]);
576 sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
580 i810EmitTexVerified(dev, sarea_priv->TexState[1]);
581 sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
592 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
593 int nbox = sarea_priv->nbox;
594 struct drm_clip_rect *pbox = sarea_priv->boxes;
665 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
666 int nbox = sarea_priv->nbox;
667 struct drm_clip_rect *pbox = sarea_priv->boxes;
713 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
714 struct drm_clip_rect *box = sarea_priv->boxes;
715 int nbox = sarea_priv->nbox;
729 if (sarea_priv->dirty)
733 unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
796 dev_priv->sarea_priv->pf_current_page);
830 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
930 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
931 dev_priv->sarea_priv;
946 sarea_priv->last_enqueue = dev_priv->counter - 1;
947 sarea_priv->last_dispatch = (int)hw_status[5];
984 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
985 dev_priv->sarea_priv;
987 sarea_priv->last_dispatch = (int)hw_status[5];
998 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
999 dev_priv->sarea_priv;
1010 sarea_priv->last_dispatch = (int)hw_status[5];
1034 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
1049 sarea_priv->dirty = 0x7f;
1093 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
1094 dev_priv->sarea_priv;
1105 sarea_priv->last_enqueue = dev_priv->counter - 1;
1106 sarea_priv->last_dispatch = (int)hw_status[5];
1162 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;