Lines Matching defs:obj
38 struct drm_i915_gem_object *obj;
44 list_for_each_entry(obj, &dev_priv->render_ring.active_list, list) {
45 if (obj->base.dev != dev ||
46 !atomic_read(&obj->base.refcount.refcount)) {
47 DRM_ERROR("freed render active %p\n", obj);
50 } else if (!obj->active ||
51 (obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) {
53 obj,
54 obj->active,
55 obj->base.read_domains);
57 } else if (obj->base.write_domain && list_empty(&obj->gpu_write_list)) {
59 obj,
60 obj->base.write_domain,
61 !list_empty(&obj->gpu_write_list));
66 list_for_each_entry(obj, &dev_priv->mm.flushing_list, list) {
67 if (obj->base.dev != dev ||
68 !atomic_read(&obj->base.refcount.refcount)) {
69 DRM_ERROR("freed flushing %p\n", obj);
72 } else if (!obj->active ||
73 (obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0 ||
74 list_empty(&obj->gpu_write_list)) {
76 obj,
77 obj->active,
78 obj->base.write_domain,
79 !list_empty(&obj->gpu_write_list));
84 list_for_each_entry(obj, &dev_priv->mm.gpu_write_list, gpu_write_list) {
85 if (obj->base.dev != dev ||
86 !atomic_read(&obj->base.refcount.refcount)) {
87 DRM_ERROR("freed gpu write %p\n", obj);
90 } else if (!obj->active ||
91 (obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) {
93 obj,
94 obj->active,
95 obj->base.write_domain);
100 list_for_each_entry(obj, &i915_gtt_vm->inactive_list, list) {
101 if (obj->base.dev != dev ||
102 !atomic_read(&obj->base.refcount.refcount)) {
103 DRM_ERROR("freed inactive %p\n", obj);
106 } else if (obj->pin_count || obj->active ||
107 (obj->base.write_domain & I915_GEM_GPU_DOMAINS)) {
109 obj,
110 obj->pin_count, obj->active,
111 obj->base.write_domain);