Lines Matching defs:intel_dp
89 * @intel_dp: DP struct
94 static bool is_edp(struct intel_dp *intel_dp)
96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
101 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
108 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
113 static void intel_dp_link_down(struct intel_dp *intel_dp);
114 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
115 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
118 intel_dp_max_link_bw(struct intel_dp *intel_dp)
120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
144 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
193 struct intel_dp *intel_dp = intel_attached_dp(connector);
199 if (is_edp(intel_dp) && fixed_mode) {
209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
210 max_lanes = intel_dp_max_lane_count(intel_dp);
286 struct intel_dp *intel_dp,
290 struct intel_dp *intel_dp,
293 static void pps_lock(struct intel_dp *intel_dp)
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
311 static void pps_unlock(struct intel_dp *intel_dp)
313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
326 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
337 if (intel_dp->pps_pipe != INVALID_PIPE)
338 return intel_dp->pps_pipe;
346 struct intel_dp *tmp;
364 intel_dp->pps_pipe = ffs(pipes) - 1;
367 pipe_name(intel_dp->pps_pipe),
371 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
372 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
375 return intel_dp->pps_pipe;
423 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
435 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
438 if (intel_dp->pps_pipe == INVALID_PIPE)
439 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
442 if (intel_dp->pps_pipe == INVALID_PIPE)
443 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
447 if (intel_dp->pps_pipe == INVALID_PIPE) {
454 port_name(port), pipe_name(intel_dp->pps_pipe));
456 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
457 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
480 struct intel_dp *intel_dp;
485 intel_dp = enc_to_intel_dp(&encoder->base);
486 intel_dp->pps_pipe = INVALID_PIPE;
490 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
492 struct drm_device *dev = intel_dp_to_dev(intel_dp);
497 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
500 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
502 struct drm_device *dev = intel_dp_to_dev(intel_dp);
507 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
515 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
522 if (!is_edp(intel_dp) || code != SYS_RESTART)
525 pps_lock(intel_dp);
528 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
538 msleep(intel_dp->panel_power_cycle_delay);
541 pps_unlock(intel_dp);
546 static bool edp_have_panel_power(struct intel_dp *intel_dp)
548 struct drm_device *dev = intel_dp_to_dev(intel_dp);
553 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
556 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
563 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
567 intel_dp_check_edp(struct intel_dp *intel_dp)
569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
572 if (!is_edp(intel_dp))
575 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
578 I915_READ(_pp_stat_reg(intel_dp)),
579 I915_READ(_pp_ctrl_reg(intel_dp)));
584 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
589 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
607 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
609 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
619 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
621 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
637 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
639 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
659 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
664 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
678 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
695 intel_dp_aux_ch(struct intel_dp *intel_dp,
699 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
702 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
711 pps_lock(intel_dp);
719 vdd = edp_panel_vdd_on(intel_dp);
727 intel_dp_check_edp(intel_dp);
752 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
753 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
768 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
826 edp_panel_vdd_off(intel_dp, false);
828 pps_unlock(intel_dp);
838 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
859 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
876 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
899 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
901 struct drm_device *dev = intel_dp_to_dev(intel_dp);
902 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
909 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
913 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
917 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
921 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
929 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
931 intel_dp->aux.name = name;
932 intel_dp->aux.dev = dev->dev;
933 intel_dp->aux.transfer = intel_dp_aux_transfer;
938 ret = drm_dp_aux_register(&intel_dp->aux);
946 &intel_dp->aux.ddc.dev.kobj,
947 intel_dp->aux.ddc.dev.kobj.name);
950 drm_dp_aux_unregister(&intel_dp->aux);
957 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
961 intel_dp->aux.ddc.dev.kobj.name);
1021 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1022 enum port port = dp_to_dig_port(intel_dp)->port;
1024 struct intel_connector *intel_connector = intel_dp->attached_connector;
1027 int max_lane_count = intel_dp_max_lane_count(intel_dp);
1030 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
1040 pipe_config->has_audio = intel_dp->has_audio;
1042 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1064 if (is_edp(intel_dp)) {
1102 if (intel_dp->color_range_auto) {
1109 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1111 intel_dp->color_range = 0;
1114 if (intel_dp->color_range)
1117 intel_dp->link_bw = bws[clock];
1118 intel_dp->lane_count = lane_count;
1120 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
1123 intel_dp->link_bw, intel_dp->lane_count,
1134 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
1143 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1145 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
1150 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1152 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1168 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1171 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1184 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1185 enum port port = dp_to_dig_port(intel_dp)->port;
1209 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1212 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1213 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1218 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1226 intel_dp->DP |= DP_SYNC_HS_HIGH;
1228 intel_dp->DP |= DP_SYNC_VS_HIGH;
1229 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1231 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1232 intel_dp->DP |= DP_ENHANCED_FRAMING;
1234 intel_dp->DP |= crtc->pipe << 29;
1237 intel_dp->DP |= intel_dp->color_range;
1240 intel_dp->DP |= DP_SYNC_HS_HIGH;
1242 intel_dp->DP |= DP_SYNC_VS_HIGH;
1243 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1245 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1246 intel_dp->DP |= DP_ENHANCED_FRAMING;
1250 intel_dp->DP |= DP_PIPEB_SELECT;
1252 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1255 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1268 static void wait_panel_status(struct intel_dp *intel_dp,
1272 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1278 pp_stat_reg = _pp_stat_reg(intel_dp);
1279 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1295 static void wait_panel_on(struct intel_dp *intel_dp)
1298 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1301 static void wait_panel_off(struct intel_dp *intel_dp)
1304 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1307 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1313 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1314 intel_dp->panel_power_cycle_delay);
1316 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1319 static void wait_backlight_on(struct intel_dp *intel_dp)
1321 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1322 intel_dp->backlight_on_delay);
1325 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1327 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1328 intel_dp->backlight_off_delay);
1335 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1337 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1343 control = I915_READ(_pp_ctrl_reg(intel_dp));
1354 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1356 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1363 bool need_to_disable = !intel_dp->want_panel_vdd;
1367 if (!is_edp(intel_dp))
1370 intel_dp->want_panel_vdd = true;
1372 if (edp_have_panel_vdd(intel_dp))
1380 if (!edp_have_panel_power(intel_dp))
1381 wait_panel_power_cycle(intel_dp);
1383 pp = ironlake_get_pp_control(intel_dp);
1386 pp_stat_reg = _pp_stat_reg(intel_dp);
1387 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1396 if (!edp_have_panel_power(intel_dp)) {
1398 msleep(intel_dp->panel_power_up_delay);
1411 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1415 if (!is_edp(intel_dp))
1418 pps_lock(intel_dp);
1419 vdd = edp_panel_vdd_on(intel_dp);
1420 pps_unlock(intel_dp);
1425 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1427 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1430 dp_to_dig_port(intel_dp);
1438 WARN_ON(intel_dp->want_panel_vdd);
1440 if (!edp_have_panel_vdd(intel_dp))
1445 pp = ironlake_get_pp_control(intel_dp);
1448 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1449 pp_stat_reg = _pp_stat_reg(intel_dp);
1459 intel_dp->last_power_cycle = jiffies;
1467 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1468 struct intel_dp, panel_vdd_work);
1470 pps_lock(intel_dp);
1471 if (!intel_dp->want_panel_vdd)
1472 edp_panel_vdd_off_sync(intel_dp);
1473 pps_unlock(intel_dp);
1476 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1485 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1486 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1494 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1497 intel_dp_to_dev(intel_dp)->dev_private;
1501 if (!is_edp(intel_dp))
1504 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1506 intel_dp->want_panel_vdd = false;
1509 edp_panel_vdd_off_sync(intel_dp);
1511 edp_panel_vdd_schedule_off(intel_dp);
1520 static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1522 if (!is_edp(intel_dp))
1525 pps_lock(intel_dp);
1526 edp_panel_vdd_off(intel_dp, sync);
1527 pps_unlock(intel_dp);
1530 void intel_edp_panel_on(struct intel_dp *intel_dp)
1532 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1537 if (!is_edp(intel_dp))
1542 pps_lock(intel_dp);
1544 if (edp_have_panel_power(intel_dp)) {
1549 wait_panel_power_cycle(intel_dp);
1551 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1552 pp = ironlake_get_pp_control(intel_dp);
1567 wait_panel_on(intel_dp);
1568 intel_dp->last_power_on = jiffies;
1577 pps_unlock(intel_dp);
1580 void intel_edp_panel_off(struct intel_dp *intel_dp)
1582 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1584 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1590 if (!is_edp(intel_dp))
1595 pps_lock(intel_dp);
1597 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1599 pp = ironlake_get_pp_control(intel_dp);
1605 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1607 intel_dp->want_panel_vdd = false;
1612 intel_dp->last_power_cycle = jiffies;
1613 wait_panel_off(intel_dp);
1619 pps_unlock(intel_dp);
1623 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1625 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1637 wait_backlight_on(intel_dp);
1639 pps_lock(intel_dp);
1641 pp = ironlake_get_pp_control(intel_dp);
1644 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1649 pps_unlock(intel_dp);
1653 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1655 if (!is_edp(intel_dp))
1660 intel_panel_enable_backlight(intel_dp->attached_connector);
1661 _intel_edp_backlight_on(intel_dp);
1665 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
1667 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1672 if (!is_edp(intel_dp))
1675 pps_lock(intel_dp);
1677 pp = ironlake_get_pp_control(intel_dp);
1680 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1685 pps_unlock(intel_dp);
1687 intel_dp->last_backlight_off = jiffies;
1688 edp_wait_backlight_off(intel_dp);
1692 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1694 if (!is_edp(intel_dp))
1699 _intel_edp_backlight_off(intel_dp);
1700 intel_panel_disable_backlight(intel_dp->attached_connector);
1710 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1713 pps_lock(intel_dp);
1714 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1715 pps_unlock(intel_dp);
1724 _intel_edp_backlight_on(intel_dp);
1726 _intel_edp_backlight_off(intel_dp);
1729 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1731 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1745 /* We don't adjust intel_dp->DP while tearing down the link, to
1748 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1749 intel_dp->DP |= DP_PLL_ENABLE;
1750 I915_WRITE(DP_A, intel_dp->DP);
1755 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1757 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1772 * intel_dp->DP because link_down must not change that (otherwise link
1781 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1786 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1790 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1798 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1814 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1815 enum port port = dp_to_dig_port(intel_dp)->port;
1825 tmp = I915_READ(intel_dp->output_reg);
1841 switch (intel_dp->output_reg) {
1864 intel_dp->output_reg);
1873 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1877 enum port port = dp_to_dig_port(intel_dp)->port;
1881 tmp = I915_READ(intel_dp->output_reg);
1933 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1954 static bool is_edp_psr(struct intel_dp *intel_dp)
1956 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1969 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1972 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1998 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
2000 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2010 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2017 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2019 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2027 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2033 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
2034 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2037 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2050 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2052 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2064 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2080 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2082 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2124 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2126 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2135 intel_edp_psr_enable_sink(intel_dp);
2138 intel_edp_psr_enable_source(intel_dp);
2143 void intel_edp_psr_enable(struct intel_dp *intel_dp)
2145 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2153 if (!is_edp_psr(intel_dp)) {
2168 intel_edp_psr_setup(intel_dp);
2170 if (intel_edp_psr_match_conditions(intel_dp))
2171 dev_priv->psr.enabled = intel_dp;
2175 void intel_edp_psr_disable(struct intel_dp *intel_dp)
2177 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2210 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2213 intel_dp = dev_priv->psr.enabled;
2215 if (!intel_dp)
2226 intel_edp_psr_do_enable(intel_dp);
2314 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2319 intel_edp_panel_vdd_on(intel_dp);
2320 intel_edp_backlight_off(intel_dp);
2321 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2322 intel_edp_panel_off(intel_dp);
2326 intel_dp_link_down(intel_dp);
2331 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2332 enum port port = dp_to_dig_port(intel_dp)->port;
2334 intel_dp_link_down(intel_dp);
2336 ironlake_edp_pll_off(intel_dp);
2341 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2343 intel_dp_link_down(intel_dp);
2348 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2349 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2358 intel_dp_link_down(intel_dp);
2383 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2387 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2465 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2467 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2470 intel_dp->DP |= DP_PORT_EN;
2473 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2476 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2477 POSTING_READ(intel_dp->output_reg);
2482 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2485 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2490 intel_dp_enable_port(intel_dp);
2491 intel_edp_panel_vdd_on(intel_dp);
2492 intel_edp_panel_on(intel_dp);
2493 intel_edp_panel_vdd_off(intel_dp, true);
2494 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2495 intel_dp_start_link_train(intel_dp);
2496 intel_dp_complete_link_train(intel_dp);
2497 intel_dp_stop_link_train(intel_dp);
2502 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2505 intel_edp_backlight_on(intel_dp);
2510 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2512 intel_edp_backlight_on(intel_dp);
2517 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2518 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2524 ironlake_set_pll_cpu_edp(intel_dp);
2525 ironlake_edp_pll_on(intel_dp);
2539 struct intel_dp *intel_dp;
2545 intel_dp = enc_to_intel_dp(&encoder->base);
2546 port = dp_to_dig_port(intel_dp)->port;
2548 if (intel_dp->pps_pipe != pipe)
2555 edp_panel_vdd_off_sync(intel_dp);
2557 intel_dp->pps_pipe = INVALID_PIPE;
2561 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2563 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2572 if (intel_dp->pps_pipe == crtc->pipe)
2580 if (intel_dp->pps_pipe != INVALID_PIPE)
2581 edp_panel_vdd_off_sync(intel_dp);
2590 intel_dp->pps_pipe = crtc->pipe;
2593 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2596 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2597 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2603 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2604 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2627 if (is_edp(intel_dp)) {
2628 pps_lock(intel_dp);
2629 vlv_init_panel_power_sequencer(intel_dp);
2630 pps_unlock(intel_dp);
2670 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2671 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2718 if (is_edp(intel_dp)) {
2719 pps_lock(intel_dp);
2720 vlv_init_panel_power_sequencer(intel_dp);
2721 pps_unlock(intel_dp);
2831 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2833 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2841 intel_dp_voltage_max(struct intel_dp *intel_dp)
2843 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2844 enum port port = dp_to_dig_port(intel_dp)->port;
2857 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2859 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2860 enum port port = dp_to_dig_port(intel_dp)->port;
2911 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2913 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2915 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2920 uint8_t train_set = intel_dp->train_set[0];
3011 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3013 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3015 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3018 uint8_t train_set = intel_dp->train_set[0];
3172 intel_get_adjust_train(struct intel_dp *intel_dp,
3181 for (lane = 0; lane < intel_dp->lane_count; lane++) {
3191 voltage_max = intel_dp_voltage_max(intel_dp);
3195 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3200 intel_dp->train_set[lane] = v | p;
3336 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3338 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3342 uint8_t train_set = intel_dp->train_set[0];
3348 signal_levels = intel_chv_signal_levels(intel_dp);
3351 signal_levels = intel_vlv_signal_levels(intel_dp);
3370 intel_dp_set_link_train(struct intel_dp *intel_dp,
3374 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3377 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3380 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3382 I915_WRITE(intel_dp->output_reg, *DP);
3383 POSTING_READ(intel_dp->output_reg);
3392 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3393 len = intel_dp->lane_count + 1;
3396 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3403 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3406 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3407 intel_dp_set_signal_levels(intel_dp, DP);
3408 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3412 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3415 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3420 intel_get_adjust_train(intel_dp, link_status);
3421 intel_dp_set_signal_levels(intel_dp, DP);
3423 I915_WRITE(intel_dp->output_reg, *DP);
3424 POSTING_READ(intel_dp->output_reg);
3426 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3427 intel_dp->train_set, intel_dp->lane_count);
3429 return ret == intel_dp->lane_count;
3432 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3434 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3465 intel_dp_start_link_train(struct intel_dp *intel_dp)
3467 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3472 uint32_t DP = intel_dp->DP;
3479 link_config[0] = intel_dp->link_bw;
3480 link_config[1] = intel_dp->lane_count;
3481 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3483 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3487 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3492 if (!intel_dp_reset_link_train(intel_dp, &DP,
3505 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3506 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3511 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3517 for (i = 0; i < intel_dp->lane_count; i++)
3518 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3520 if (i == intel_dp->lane_count) {
3526 intel_dp_reset_link_train(intel_dp, &DP,
3534 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3542 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3545 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3551 intel_dp->DP = DP;
3555 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3559 uint32_t DP = intel_dp->DP;
3563 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3567 if (!intel_dp_set_link_train(intel_dp, &DP,
3585 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3586 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3592 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3593 intel_dp_start_link_train(intel_dp);
3594 intel_dp_set_link_train(intel_dp, &DP,
3601 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3608 intel_dp_link_down(intel_dp);
3609 intel_dp_start_link_train(intel_dp);
3610 intel_dp_set_link_train(intel_dp, &DP,
3619 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3626 intel_dp_set_idle_link_train(intel_dp);
3628 intel_dp->DP = DP;
3635 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3637 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3642 intel_dp_link_down(struct intel_dp *intel_dp)
3644 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3650 uint32_t DP = intel_dp->DP;
3655 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3662 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3668 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3670 POSTING_READ(intel_dp->output_reg);
3673 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3685 I915_WRITE(intel_dp->output_reg, DP);
3694 POSTING_READ(intel_dp->output_reg);
3701 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3702 POSTING_READ(intel_dp->output_reg);
3703 msleep(intel_dp->panel_power_down_delay);
3707 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3709 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3713 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3714 sizeof(intel_dp->dpcd)) < 0)
3717 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3719 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3723 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3724 if (is_edp(intel_dp)) {
3725 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3726 intel_dp->psr_dpcd,
3727 sizeof(intel_dp->psr_dpcd));
3728 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3735 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3736 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3738 intel_dp->use_tps3 = true;
3741 intel_dp->use_tps3 = false;
3743 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3747 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3750 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3751 intel_dp->downstream_ports,
3759 intel_dp_probe_oui(struct intel_dp *intel_dp)
3763 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3766 intel_edp_panel_vdd_on(intel_dp);
3768 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3772 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3776 intel_edp_panel_vdd_off(intel_dp, false);
3780 intel_dp_probe_mst(struct intel_dp *intel_dp)
3784 if (!intel_dp->can_mst)
3787 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3790 intel_edp_panel_vdd_on(intel_dp);
3791 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3794 intel_dp->is_mst = true;
3797 intel_dp->is_mst = false;
3800 intel_edp_panel_vdd_off(intel_dp, false);
3802 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3803 return intel_dp->is_mst;
3806 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3808 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3814 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3820 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3828 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3831 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3836 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3838 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3844 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3848 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3858 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3861 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3865 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3869 if (intel_dp->is_mst) {
3874 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3879 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3881 intel_dp_start_link_train(intel_dp);
3882 intel_dp_complete_link_train(intel_dp);
3883 intel_dp_stop_link_train(intel_dp);
3887 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3892 wret = drm_dp_dpcd_write(&intel_dp->aux,
3900 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3910 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3912 intel_dp->is_mst = false;
3913 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3930 intel_dp_check_link_status(struct intel_dp *intel_dp)
3932 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3933 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3949 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3954 if (!intel_dp_get_dpcd(intel_dp)) {
3959 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3960 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3962 drm_dp_dpcd_writeb(&intel_dp->aux,
3967 intel_dp_handle_test_request(intel_dp);
3972 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3975 intel_dp_start_link_train(intel_dp);
3976 intel_dp_complete_link_train(intel_dp);
3977 intel_dp_stop_link_train(intel_dp);
3983 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3985 uint8_t *dpcd = intel_dp->dpcd;
3988 if (!intel_dp_get_dpcd(intel_dp))
3996 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3997 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4000 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4009 if (drm_probe_ddc(&intel_dp->aux.ddc))
4013 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4014 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4019 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4032 edp_detect(struct intel_dp *intel_dp)
4034 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4045 ironlake_dp_detect(struct intel_dp *intel_dp)
4047 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4049 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4054 return intel_dp_detect_dpcd(intel_dp);
4099 g4x_dp_detect(struct intel_dp *intel_dp)
4101 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4102 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4106 if (is_edp(intel_dp)) {
4121 return intel_dp_detect_dpcd(intel_dp);
4125 intel_dp_get_edid(struct intel_dp *intel_dp)
4127 struct intel_connector *intel_connector = intel_dp->attached_connector;
4138 &intel_dp->aux.ddc);
4142 intel_dp_set_edid(struct intel_dp *intel_dp)
4144 struct intel_connector *intel_connector = intel_dp->attached_connector;
4147 edid = intel_dp_get_edid(intel_dp);
4150 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4151 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4153 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4157 intel_dp_unset_edid(struct intel_dp *intel_dp)
4159 struct intel_connector *intel_connector = intel_dp->attached_connector;
4164 intel_dp->has_audio = false;
4168 intel_dp_power_get(struct intel_dp *dp)
4180 intel_dp_power_put(struct intel_dp *dp,
4190 struct intel_dp *intel_dp = intel_attached_dp(connector);
4191 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4200 intel_dp_unset_edid(intel_dp);
4202 if (intel_dp->is_mst) {
4209 power_domain = intel_dp_power_get(intel_dp);
4212 if (is_edp(intel_dp))
4213 status = edp_detect(intel_dp);
4215 status = ironlake_dp_detect(intel_dp);
4217 status = g4x_dp_detect(intel_dp);
4221 intel_dp_probe_oui(intel_dp);
4223 ret = intel_dp_probe_mst(intel_dp);
4233 intel_dp_set_edid(intel_dp);
4240 intel_dp_power_put(intel_dp, power_domain);
4247 struct intel_dp *intel_dp = intel_attached_dp(connector);
4248 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4253 intel_dp_unset_edid(intel_dp);
4258 power_domain = intel_dp_power_get(intel_dp);
4260 intel_dp_set_edid(intel_dp);
4262 intel_dp_power_put(intel_dp, power_domain);
4317 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4328 if (i == intel_dp->force_audio)
4331 intel_dp->force_audio = i;
4338 if (has_audio == intel_dp->has_audio)
4341 intel_dp->has_audio = has_audio;
4346 bool old_auto = intel_dp->color_range_auto;
4347 uint32_t old_range = intel_dp->color_range;
4351 intel_dp->color_range_auto = true;
4354 intel_dp->color_range_auto = false;
4355 intel_dp->color_range = 0;
4358 intel_dp->color_range_auto = false;
4359 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4365 if (old_auto == intel_dp->color_range_auto &&
4366 old_range == intel_dp->color_range)
4372 if (is_edp(intel_dp) &&
4419 struct intel_dp *intel_dp = &intel_dig_port->dp;
4421 drm_dp_aux_unregister(&intel_dp->aux);
4424 if (is_edp(intel_dp)) {
4425 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4430 pps_lock(intel_dp);
4431 edp_panel_vdd_off_sync(intel_dp);
4432 pps_unlock(intel_dp);
4434 if (intel_dp->edp_notifier.notifier_call) {
4435 unregister_reboot_notifier(&intel_dp->edp_notifier);
4436 intel_dp->edp_notifier.notifier_call = NULL;
4444 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4446 if (!is_edp(intel_dp))
4453 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4454 pps_lock(intel_dp);
4455 edp_panel_vdd_off_sync(intel_dp);
4456 pps_unlock(intel_dp);
4493 struct intel_dp *intel_dp = &intel_dig_port->dp;
4532 if (!intel_dp_get_dpcd(intel_dp)) {
4536 intel_dp_probe_oui(intel_dp);
4538 if (!intel_dp_probe_mst(intel_dp))
4542 if (intel_dp->is_mst) {
4543 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4547 if (!intel_dp->is_mst) {
4553 intel_dp_check_link_status(intel_dp);
4561 if (intel_dp->is_mst) {
4562 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4563 intel_dp->is_mst = false;
4564 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4578 struct intel_dp *intel_dp;
4581 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4585 return intel_dp->output_reg;
4621 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4627 intel_dp->color_range_auto = true;
4629 if (is_edp(intel_dp)) {
4639 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4641 intel_dp->last_power_cycle = jiffies;
4642 intel_dp->last_power_on = jiffies;
4643 intel_dp->last_backlight_off = jiffies;
4648 struct intel_dp *intel_dp,
4664 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4674 pp = ironlake_get_pp_control(intel_dp);
4730 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4731 intel_dp->backlight_on_delay = get_delay(t8);
4732 intel_dp->backlight_off_delay = get_delay(t9);
4733 intel_dp->panel_power_down_delay = get_delay(t10);
4734 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4738 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4739 intel_dp->panel_power_cycle_delay);
4742 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4750 struct intel_dp *intel_dp,
4757 enum port port = dp_to_dig_port(intel_dp)->port;
4766 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4818 struct intel_dp *intel_dp = NULL;
4846 intel_dp = enc_to_intel_dp(&encoder->base);
4856 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4864 if (index == intel_dp->drrs_state.refresh_rate_type) {
4894 mutex_lock(&intel_dp->drrs_state.mutex);
4896 intel_dp->drrs_state.refresh_rate_type = index;
4898 mutex_unlock(&intel_dp->drrs_state.mutex);
4909 struct intel_dp *intel_dp = &intel_dig_port->dp;
4934 mutex_init(&intel_dp->drrs_state.mutex);
4936 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4938 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4947 struct intel_dp *intel_dp;
4953 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4955 pps_lock(intel_dp);
4957 if (!edp_have_panel_vdd(intel_dp))
4969 edp_panel_vdd_schedule_off(intel_dp);
4971 pps_unlock(intel_dp);
4974 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4979 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4989 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4991 if (!is_edp(intel_dp))
4997 intel_edp_panel_vdd_on(intel_dp);
4998 has_dpcd = intel_dp_get_dpcd(intel_dp);
4999 intel_edp_panel_vdd_off(intel_dp, false);
5002 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5004 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5013 pps_lock(intel_dp);
5014 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
5015 pps_unlock(intel_dp);
5018 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5054 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5055 register_reboot_notifier(&intel_dp->edp_notifier);
5070 struct intel_dp *intel_dp = &intel_dig_port->dp;
5078 intel_dp->pps_pipe = INVALID_PIPE;
5080 /* intel_dp vfuncs */
5082 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5084 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5086 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5088 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5090 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5093 intel_dp->DP = I915_READ(intel_dp->output_reg);
5094 intel_dp->attached_connector = intel_connector;
5119 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5149 if (is_edp(intel_dp)) {
5150 pps_lock(intel_dp);
5152 vlv_initial_power_sequencer_setup(intel_dp);
5154 intel_dp_init_panel_power_timestamps(intel_dp);
5155 intel_dp_init_panel_power_sequencer(dev, intel_dp,
5158 pps_unlock(intel_dp);
5161 intel_dp_aux_init(intel_dp, intel_connector);
5171 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
5172 drm_dp_aux_unregister(&intel_dp->aux);
5173 if (is_edp(intel_dp)) {
5174 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5179 pps_lock(intel_dp);
5180 edp_panel_vdd_off_sync(intel_dp);
5181 pps_unlock(intel_dp);
5188 intel_dp_add_properties(intel_dp, connector);