Cross Reference: /drivers/gpu/drm/i915/intel_dsi

Lines Matching refs:pipe
57 	enum pipe pipe = intel_crtc->pipe;
60 	val = I915_READ(MIPI_INTR_STAT(pipe));
65 		      "\n", pipe, val,
113 	enum pipe pipe = intel_crtc->pipe;
117 	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50))
120 	temp = I915_READ(MIPI_HS_LP_DBI_ENABLE(pipe));
122 	I915_WRITE(MIPI_HS_LP_DBI_ENABLE(pipe), enable ? DBI_HS_MODE : DBI_LP_MODE);
134 	enum pipe pipe = intel_crtc->pipe;
143 		ctrl_reg = MIPI_HS_GEN_CTRL(pipe);
146 		ctrl_reg = MIPI_LP_GEN_CTRL(pipe);
150 	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50)) {
176 	enum pipe pipe = intel_crtc->pipe;
185 		data_reg = MIPI_HS_GEN_DATA(pipe);
188 		data_reg = MIPI_LP_GEN_DATA(pipe);
192 	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50))
295 	enum pipe pipe = intel_crtc->pipe;
300 		data_reg = MIPI_HS_GEN_DATA(pipe);
302 		data_reg = MIPI_LP_GEN_DATA(pipe);
321 	enum pipe pipe = intel_crtc->pipe;
330 	I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL);
337 	if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50))
357 	enum pipe pipe = intel_crtc->pipe;
366 	I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL);
374 	if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50))
398 	enum pipe pipe = intel_crtc->pipe;
401 	/* XXX: pipe, hs */
408 	I915_WRITE(MIPI_INTR_STAT(pipe), SPL_PKT_SENT_INTERRUPT);
411 	if (cmd == I915_READ(MIPI_DPI_CONTROL(pipe)))
414 	I915_WRITE(MIPI_DPI_CONTROL(pipe), cmd);
417 	if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 100))
429 	enum pipe pipe = intel_crtc->pipe;
435 	if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 100))