Cross Reference: /drivers/gpu/drm/i915/intel

Lines Matching defs:dev_priv
49 	struct drm_i915_private *dev_priv = dev->dev_private;
117 				  struct drm_i915_private *dev_priv)
138 	struct drm_i915_private *dev_priv = dev->dev_private;
175 	struct drm_i915_private *dev_priv = dev->dev_private;
213 	struct drm_i915_private *dev_priv = dev->dev_private;
254 	struct drm_i915_private *dev_priv = dev->dev_private;
292 	struct drm_i915_private *dev_priv = dev->dev_private;
301 					  dev_priv);
427 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
481 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
529 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
566 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
614 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
642 	struct drm_i915_private *dev_priv = dev->dev_private;
687 	struct drm_i915_private *dev_priv = dev->dev_private;
693 	if (!intel_display_power_enabled(dev_priv, power_domain))
716 	struct drm_i915_private *dev_priv = dev->dev_private;
749 	if (HAS_PCH_SPLIT(dev_priv->dev))
758 	struct drm_i915_private *dev_priv = dev->dev_private;
803 	struct drm_i915_private *dev_priv = dev->dev_private;
995 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
1004 	intel_display_power_get(dev_priv, power_domain);
1007 			    intel_gmbus_get_adapter(dev_priv,
1010 	intel_display_power_put(dev_priv, power_domain);
1102 	struct drm_i915_private *dev_priv = connector->dev->dev_private;
1109 	if (property == dev_priv->force_audio_property) {
1130 	if (property == dev_priv->broadcast_rgb_property) {
1202 	struct drm_i915_private *dev_priv = dev->dev_private;
1212 	mutex_lock(&dev_priv->dpio_lock);
1213 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1220 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1223 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1224 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1225 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1226 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1227 	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1228 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1229 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1230 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1233 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1234 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1235 	mutex_unlock(&dev_priv->dpio_lock);
1243 	vlv_wait_port_ready(dev_priv, dport);
1250 	struct drm_i915_private *dev_priv = dev->dev_private;
1259 	mutex_lock(&dev_priv->dpio_lock);
1260 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1263 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1270 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1271 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1272 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1274 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1275 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1276 	mutex_unlock(&dev_priv->dpio_lock);
1283 	struct drm_i915_private *dev_priv = dev->dev_private;
1292 	mutex_lock(&dev_priv->dpio_lock);
1296 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1302 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1304 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1310 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1314 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1320 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1322 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1328 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1335 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1340 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1342 	mutex_unlock(&dev_priv->dpio_lock);
1348 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1355 	mutex_lock(&dev_priv->dpio_lock);
1356 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1357 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1358 	mutex_unlock(&dev_priv->dpio_lock);
1365 	struct drm_i915_private *dev_priv = dev->dev_private;
1372 	mutex_lock(&dev_priv->dpio_lock);
1375 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1377 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1379 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1381 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1383 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1385 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1387 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1389 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1391 	mutex_unlock(&dev_priv->dpio_lock);
1398 	struct drm_i915_private *dev_priv = dev->dev_private;
1406 	mutex_lock(&dev_priv->dpio_lock);
1409 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1411 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1413 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1415 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1417 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1419 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1421 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1423 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1429 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
1434 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1442 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1444 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1446 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1448 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1453 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1456 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1460 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1463 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1468 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1470 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1475 	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1480 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1482 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
1483 			vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
1487 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1489 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1491 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1493 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1496 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1498 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1500 	mutex_unlock(&dev_priv->dpio_lock);
1504 	vlv_wait_port_ready(dev_priv, dport);
1559 	struct drm_i915_private *dev_priv = dev->dev_private;