Cross Reference: /drivers/gpu/drm/nouveau/core/subdev/i2c/anx9805.c

Lines Matching refs:addr
29 	u32 addr;
42 	nv_wri2cr(mast, chan->addr, 0xa0, link_bw);
43 	nv_wri2cr(mast, chan->addr, 0xa1, link_nr | (enh ? 0x80 : 0x00));
44 	nv_wri2cr(mast, chan->addr, 0xa2, 0x01);
45 	nv_wri2cr(mast, chan->addr, 0xa8, 0x01);
48 	while ((tmp = nv_rdi2cr(mast, chan->addr, 0xa8)) & 0x01) {
66 	    u8 type, u32 addr, u8 *data, u8 size)
74 	DBG("%02x %05x %d\n", type, addr, size);
81 	nv_wri2cr(mast, chan->addr, 0xe4, 0x80);
86 			nv_wri2cr(mast, chan->addr, 0xf0 + i, buf[i]);
88 	nv_wri2cr(mast, chan->addr, 0xe5, ((size - 1) << 4) | type);
89 	nv_wri2cr(mast, chan->addr, 0xe6, (addr & 0x000ff) >>  0);
90 	nv_wri2cr(mast, chan->addr, 0xe7, (addr & 0x0ff00) >>  8);
91 	nv_wri2cr(mast, chan->addr, 0xe8, (addr & 0xf0000) >> 16);
92 	nv_wri2cr(mast, chan->addr, 0xe9, 0x01);
95 	while ((tmp = nv_rdi2cr(mast, chan->addr, 0xe9)) & 0x01) {
108 			buf[i] = nv_rdi2cr(mast, chan->addr, 0xf0 + i);
144 		chan->addr = 0x38;
148 		chan->addr = 0x3c;
183 	nv_wri2cr(mast, port->addr, 0x43, 0x05);
187 		if ( (msg->flags & I2C_M_RD) && msg->addr == 0x50) {
188 			nv_wri2cr(mast, port->addr, 0x40, msg->addr << 1);
189 			nv_wri2cr(mast, port->addr, 0x41, seg);
190 			nv_wri2cr(mast, port->addr, 0x42, off);
191 			nv_wri2cr(mast, port->addr, 0x44, msg->len);
192 			nv_wri2cr(mast, port->addr, 0x45, 0x00);
193 			nv_wri2cr(mast, port->addr, 0x43, 0x01);
196 				while (nv_rdi2cr(mast, port->addr, 0x46) & 0x10) {
201 				msg->buf[i] = nv_rdi2cr(mast, port->addr, 0x47);
205 			if (msg->addr == 0x50 && msg->len == 0x01) {
208 			if (msg->addr == 0x30 && msg->len == 0x01) {
220 	nv_wri2cr(mast, port->addr, 0x43, 0x00);
259 		port->addr = 0x3d;
263 		port->addr = 0x3f;