Lines Matching refs:rdev
36 static int kv_enable_nb_dpm(struct radeon_device *rdev,
38 static void kv_init_graphics_levels(struct radeon_device *rdev);
39 static int kv_calculate_ds_divider(struct radeon_device *rdev);
40 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev);
41 static int kv_calculate_dpm_settings(struct radeon_device *rdev);
42 static void kv_enable_new_levels(struct radeon_device *rdev);
43 static void kv_program_nbps_index_settings(struct radeon_device *rdev,
45 static int kv_set_enabled_level(struct radeon_device *rdev, u32 level);
46 static int kv_set_enabled_levels(struct radeon_device *rdev);
47 static int kv_force_dpm_highest(struct radeon_device *rdev);
48 static int kv_force_dpm_lowest(struct radeon_device *rdev);
49 static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
52 static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
54 static int kv_init_fps_limits(struct radeon_device *rdev);
56 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
57 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate);
58 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate);
59 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate);
61 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
62 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
63 extern void cik_update_cg(struct radeon_device *rdev,
249 static struct kv_power_info *kv_get_pi(struct radeon_device *rdev)
251 struct kv_power_info *pi = rdev->pm.dpm.priv;
257 static void kv_program_local_cac_table(struct radeon_device *rdev,
282 static int kv_program_pt_config_registers(struct radeon_device *rdev,
331 static void kv_do_enable_didt(struct radeon_device *rdev, bool enable)
333 struct kv_power_info *pi = kv_get_pi(rdev);
373 static int kv_enable_didt(struct radeon_device *rdev, bool enable)
375 struct kv_power_info *pi = kv_get_pi(rdev);
382 cik_enter_rlc_safe_mode(rdev);
385 ret = kv_program_pt_config_registers(rdev, didt_config_kv);
387 cik_exit_rlc_safe_mode(rdev);
392 kv_do_enable_didt(rdev, enable);
394 cik_exit_rlc_safe_mode(rdev);
401 static void kv_initialize_hardware_cac_manager(struct radeon_device *rdev)
403 struct kv_power_info *pi = kv_get_pi(rdev);
408 kv_program_local_cac_table(rdev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
412 kv_program_local_cac_table(rdev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
416 kv_program_local_cac_table(rdev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
420 kv_program_local_cac_table(rdev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
424 kv_program_local_cac_table(rdev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
428 kv_program_local_cac_table(rdev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
433 static int kv_enable_smc_cac(struct radeon_device *rdev, bool enable)
435 struct kv_power_info *pi = kv_get_pi(rdev);
440 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_EnableCac);
446 kv_notify_message_to_smu(rdev, PPSMC_MSG_DisableCac);
454 static int kv_process_firmware_header(struct radeon_device *rdev)
456 struct kv_power_info *pi = kv_get_pi(rdev);
460 ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
467 ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
477 static int kv_enable_dpm_voltage_scaling(struct radeon_device *rdev)
479 struct kv_power_info *pi = kv_get_pi(rdev);
484 ret = kv_copy_bytes_to_smc(rdev,
493 static int kv_set_dpm_interval(struct radeon_device *rdev)
495 struct kv_power_info *pi = kv_get_pi(rdev);
500 ret = kv_copy_bytes_to_smc(rdev,
509 static int kv_set_dpm_boot_state(struct radeon_device *rdev)
511 struct kv_power_info *pi = kv_get_pi(rdev);
514 ret = kv_copy_bytes_to_smc(rdev,
523 static void kv_program_vc(struct radeon_device *rdev)
528 static void kv_clear_vc(struct radeon_device *rdev)
533 static int kv_set_divider_value(struct radeon_device *rdev,
536 struct kv_power_info *pi = kv_get_pi(rdev);
540 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
551 static u32 kv_convert_vid2_to_vid7(struct radeon_device *rdev,
556 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
573 static u32 kv_convert_vid7_to_vid2(struct radeon_device *rdev,
578 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
597 static u16 kv_convert_8bit_index_to_voltage(struct radeon_device *rdev,
603 static u16 kv_convert_2bit_index_to_voltage(struct radeon_device *rdev,
606 struct kv_power_info *pi = kv_get_pi(rdev);
607 u32 vid_8bit = kv_convert_vid2_to_vid7(rdev,
611 return kv_convert_8bit_index_to_voltage(rdev, (u16)vid_8bit);
615 static int kv_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
617 struct kv_power_info *pi = kv_get_pi(rdev);
621 cpu_to_be32(kv_convert_2bit_index_to_voltage(rdev, vid));
626 static int kv_set_at(struct radeon_device *rdev, u32 index, u32 at)
628 struct kv_power_info *pi = kv_get_pi(rdev);
635 static void kv_dpm_power_level_enable(struct radeon_device *rdev,
638 struct kv_power_info *pi = kv_get_pi(rdev);
643 static void kv_start_dpm(struct radeon_device *rdev)
650 kv_smc_dpm_enable(rdev, true);
653 static void kv_stop_dpm(struct radeon_device *rdev)
655 kv_smc_dpm_enable(rdev, false);
658 static void kv_start_am(struct radeon_device *rdev)
668 static void kv_reset_am(struct radeon_device *rdev)
677 static int kv_freeze_sclk_dpm(struct radeon_device *rdev, bool freeze)
679 return kv_notify_message_to_smu(rdev, freeze ?
683 static int kv_force_lowest_valid(struct radeon_device *rdev)
685 return kv_force_dpm_lowest(rdev);
688 static int kv_unforce_levels(struct radeon_device *rdev)
690 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
691 return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
693 return kv_set_enabled_levels(rdev);
696 static int kv_update_sclk_t(struct radeon_device *rdev)
698 struct kv_power_info *pi = kv_get_pi(rdev);
705 ret = kv_copy_bytes_to_smc(rdev,
714 static int kv_program_bootup_state(struct radeon_device *rdev)
716 struct kv_power_info *pi = kv_get_pi(rdev);
719 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
728 kv_dpm_power_level_enable(rdev, i, true);
742 kv_dpm_power_level_enable(rdev, i, true);
747 static int kv_enable_auto_thermal_throttling(struct radeon_device *rdev)
749 struct kv_power_info *pi = kv_get_pi(rdev);
754 ret = kv_copy_bytes_to_smc(rdev,
763 static int kv_upload_dpm_settings(struct radeon_device *rdev)
765 struct kv_power_info *pi = kv_get_pi(rdev);
768 ret = kv_copy_bytes_to_smc(rdev,
778 ret = kv_copy_bytes_to_smc(rdev,
792 static u32 kv_get_clk_bypass(struct radeon_device *rdev, u32 clk)
794 struct kv_power_info *pi = kv_get_pi(rdev);
817 static int kv_populate_uvd_table(struct radeon_device *rdev)
819 struct kv_power_info *pi = kv_get_pi(rdev);
821 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
840 (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk);
842 (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk);
844 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
850 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
859 ret = kv_copy_bytes_to_smc(rdev,
869 ret = kv_copy_bytes_to_smc(rdev,
877 ret = kv_copy_bytes_to_smc(rdev,
888 static int kv_populate_vce_table(struct radeon_device *rdev)
890 struct kv_power_info *pi = kv_get_pi(rdev);
894 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
910 (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk);
912 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
921 ret = kv_copy_bytes_to_smc(rdev,
932 ret = kv_copy_bytes_to_smc(rdev,
941 ret = kv_copy_bytes_to_smc(rdev,
951 static int kv_populate_samu_table(struct radeon_device *rdev)
953 struct kv_power_info *pi = kv_get_pi(rdev);
955 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
973 (u8)kv_get_clk_bypass(rdev, table->entries[i].clk);
975 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
984 ret = kv_copy_bytes_to_smc(rdev,
995 ret = kv_copy_bytes_to_smc(rdev,
1004 ret = kv_copy_bytes_to_smc(rdev,
1017 static int kv_populate_acp_table(struct radeon_device *rdev)
1019 struct kv_power_info *pi = kv_get_pi(rdev);
1021 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1034 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1043 ret = kv_copy_bytes_to_smc(rdev,
1054 ret = kv_copy_bytes_to_smc(rdev,
1063 ret = kv_copy_bytes_to_smc(rdev,
1075 static void kv_calculate_dfs_bypass_settings(struct radeon_device *rdev)
1077 struct kv_power_info *pi = kv_get_pi(rdev);
1080 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1125 static int kv_enable_ulv(struct radeon_device *rdev, bool enable)
1127 return kv_notify_message_to_smu(rdev, enable ?
1131 static void kv_reset_acp_boot_level(struct radeon_device *rdev)
1133 struct kv_power_info *pi = kv_get_pi(rdev);
1138 static void kv_update_current_ps(struct radeon_device *rdev,
1142 struct kv_power_info *pi = kv_get_pi(rdev);
1149 static void kv_update_requested_ps(struct radeon_device *rdev,
1153 struct kv_power_info *pi = kv_get_pi(rdev);
1160 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable)
1162 struct kv_power_info *pi = kv_get_pi(rdev);
1166 ret = kv_smc_bapm_enable(rdev, enable);
1172 int kv_dpm_enable(struct radeon_device *rdev)
1174 struct kv_power_info *pi = kv_get_pi(rdev);
1177 ret = kv_process_firmware_header(rdev);
1182 kv_init_fps_limits(rdev);
1183 kv_init_graphics_levels(rdev);
1184 ret = kv_program_bootup_state(rdev);
1189 kv_calculate_dfs_bypass_settings(rdev);
1190 ret = kv_upload_dpm_settings(rdev);
1195 ret = kv_populate_uvd_table(rdev);
1200 ret = kv_populate_vce_table(rdev);
1205 ret = kv_populate_samu_table(rdev);
1210 ret = kv_populate_acp_table(rdev);
1215 kv_program_vc(rdev);
1217 kv_initialize_hardware_cac_manager(rdev);
1219 kv_start_am(rdev);
1221 ret = kv_enable_auto_thermal_throttling(rdev);
1227 ret = kv_enable_dpm_voltage_scaling(rdev);
1232 ret = kv_set_dpm_interval(rdev);
1237 ret = kv_set_dpm_boot_state(rdev);
1242 ret = kv_enable_ulv(rdev, true);
1247 kv_start_dpm(rdev);
1248 ret = kv_enable_didt(rdev, true);
1253 ret = kv_enable_smc_cac(rdev, true);
1259 kv_reset_acp_boot_level(rdev);
1261 ret = kv_smc_bapm_enable(rdev, false);
1267 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1272 int kv_dpm_late_enable(struct radeon_device *rdev)
1276 if (rdev->irq.installed &&
1277 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1278 ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1283 rdev->irq.dpm_thermal = true;
1284 radeon_irq_set(rdev);
1288 kv_dpm_powergate_acp(rdev, true);
1289 kv_dpm_powergate_samu(rdev, true);
1290 kv_dpm_powergate_vce(rdev, true);
1291 kv_dpm_powergate_uvd(rdev, true);
1296 void kv_dpm_disable(struct radeon_device *rdev)
1298 kv_smc_bapm_enable(rdev, false);
1300 if (rdev->family == CHIP_MULLINS)
1301 kv_enable_nb_dpm(rdev, false);
1304 kv_dpm_powergate_acp(rdev, false);
1305 kv_dpm_powergate_samu(rdev, false);
1306 kv_dpm_powergate_vce(rdev, false);
1307 kv_dpm_powergate_uvd(rdev, false);
1309 kv_enable_smc_cac(rdev, false);
1310 kv_enable_didt(rdev, false);
1311 kv_clear_vc(rdev);
1312 kv_stop_dpm(rdev);
1313 kv_enable_ulv(rdev, false);
1314 kv_reset_am(rdev);
1316 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1320 static int kv_write_smc_soft_register(struct radeon_device *rdev,
1323 struct kv_power_info *pi = kv_get_pi(rdev);
1325 return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset,
1329 static int kv_read_smc_soft_register(struct radeon_device *rdev,
1332 struct kv_power_info *pi = kv_get_pi(rdev);
1334 return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset,
1339 static void kv_init_sclk_t(struct radeon_device *rdev)
1341 struct kv_power_info *pi = kv_get_pi(rdev);
1346 static int kv_init_fps_limits(struct radeon_device *rdev)
1348 struct kv_power_info *pi = kv_get_pi(rdev);
1356 ret = kv_copy_bytes_to_smc(rdev,
1365 ret = kv_copy_bytes_to_smc(rdev,
1375 static void kv_init_powergate_state(struct radeon_device *rdev)
1377 struct kv_power_info *pi = kv_get_pi(rdev);
1386 static int kv_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
1388 return kv_notify_message_to_smu(rdev, enable ?
1392 static int kv_enable_vce_dpm(struct radeon_device *rdev, bool enable)
1394 return kv_notify_message_to_smu(rdev, enable ?
1398 static int kv_enable_samu_dpm(struct radeon_device *rdev, bool enable)
1400 return kv_notify_message_to_smu(rdev, enable ?
1404 static int kv_enable_acp_dpm(struct radeon_device *rdev, bool enable)
1406 return kv_notify_message_to_smu(rdev, enable ?
1410 static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate)
1412 struct kv_power_info *pi = kv_get_pi(rdev);
1414 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1430 ret = kv_copy_bytes_to_smc(rdev,
1438 kv_send_msg_to_smc_with_parameter(rdev,
1443 return kv_enable_uvd_dpm(rdev, !gate);
1446 static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk)
1450 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1460 static int kv_update_vce_dpm(struct radeon_device *rdev,
1464 struct kv_power_info *pi = kv_get_pi(rdev);
1466 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1470 kv_dpm_powergate_vce(rdev, false);
1472 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
1476 pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk);
1478 ret = kv_copy_bytes_to_smc(rdev,
1488 kv_send_msg_to_smc_with_parameter(rdev,
1492 kv_enable_vce_dpm(rdev, true);
1494 kv_enable_vce_dpm(rdev, false);
1496 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
1497 kv_dpm_powergate_vce(rdev, true);
1503 static int kv_update_samu_dpm(struct radeon_device *rdev, bool gate)
1505 struct kv_power_info *pi = kv_get_pi(rdev);
1507 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1516 ret = kv_copy_bytes_to_smc(rdev,
1526 kv_send_msg_to_smc_with_parameter(rdev,
1531 return kv_enable_samu_dpm(rdev, !gate);
1534 static u8 kv_get_acp_boot_level(struct radeon_device *rdev)
1538 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1551 static void kv_update_acp_boot_level(struct radeon_device *rdev)
1553 struct kv_power_info *pi = kv_get_pi(rdev);
1557 acp_boot_level = kv_get_acp_boot_level(rdev);
1560 kv_send_msg_to_smc_with_parameter(rdev,
1567 static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate)
1569 struct kv_power_info *pi = kv_get_pi(rdev);
1571 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1578 pi->acp_boot_level = kv_get_acp_boot_level(rdev);
1580 ret = kv_copy_bytes_to_smc(rdev,
1590 kv_send_msg_to_smc_with_parameter(rdev,
1595 return kv_enable_acp_dpm(rdev, !gate);
1598 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
1600 struct kv_power_info *pi = kv_get_pi(rdev);
1609 uvd_v1_0_stop(rdev);
1610 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, false);
1612 kv_update_uvd_dpm(rdev, gate);
1614 kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerOFF);
1617 kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerON);
1618 uvd_v4_2_resume(rdev);
1619 uvd_v1_0_start(rdev);
1620 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, true);
1622 kv_update_uvd_dpm(rdev, gate);
1626 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate)
1628 struct kv_power_info *pi = kv_get_pi(rdev);
1638 kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerOFF);
1642 kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerON);
1643 vce_v2_0_resume(rdev);
1644 vce_v1_0_start(rdev);
1649 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate)
1651 struct kv_power_info *pi = kv_get_pi(rdev);
1659 kv_update_samu_dpm(rdev, true);
1661 kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerOFF);
1664 kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerON);
1665 kv_update_samu_dpm(rdev, false);
1669 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate)
1671 struct kv_power_info *pi = kv_get_pi(rdev);
1676 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
1682 kv_update_acp_dpm(rdev, true);
1684 kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerOFF);
1687 kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerON);
1688 kv_update_acp_dpm(rdev, false);
1692 static void kv_set_valid_clock_range(struct radeon_device *rdev,
1696 struct kv_power_info *pi = kv_get_pi(rdev);
1699 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1754 static int kv_update_dfs_bypass_settings(struct radeon_device *rdev,
1758 struct kv_power_info *pi = kv_get_pi(rdev);
1765 ret = kv_copy_bytes_to_smc(rdev,
1777 static int kv_enable_nb_dpm(struct radeon_device *rdev,
1780 struct kv_power_info *pi = kv_get_pi(rdev);
1785 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);
1791 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Disable);
1800 int kv_dpm_force_performance_level(struct radeon_device *rdev,
1806 ret = kv_force_dpm_highest(rdev);
1810 ret = kv_force_dpm_lowest(rdev);
1814 ret = kv_unforce_levels(rdev);
1819 rdev->pm.dpm.forced_level = level;
1824 int kv_dpm_pre_set_power_state(struct radeon_device *rdev)
1826 struct kv_power_info *pi = kv_get_pi(rdev);
1827 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1830 kv_update_requested_ps(rdev, new_ps);
1832 kv_apply_state_adjust_rules(rdev,
1839 int kv_dpm_set_power_state(struct radeon_device *rdev)
1841 struct kv_power_info *pi = kv_get_pi(rdev);
1847 ret = kv_smc_bapm_enable(rdev, rdev->pm.dpm.ac_power);
1854 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
1856 kv_set_valid_clock_range(rdev, new_ps);
1857 kv_update_dfs_bypass_settings(rdev, new_ps);
1858 ret = kv_calculate_ds_divider(rdev);
1863 kv_calculate_nbps_level_settings(rdev);
1864 kv_calculate_dpm_settings(rdev);
1865 kv_force_lowest_valid(rdev);
1866 kv_enable_new_levels(rdev);
1867 kv_upload_dpm_settings(rdev);
1868 kv_program_nbps_index_settings(rdev, new_ps);
1869 kv_unforce_levels(rdev);
1870 kv_set_enabled_levels(rdev);
1871 kv_force_lowest_valid(rdev);
1872 kv_unforce_levels(rdev);
1874 ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1879 kv_update_sclk_t(rdev);
1880 if (rdev->family == CHIP_MULLINS)
1881 kv_enable_nb_dpm(rdev, true);
1885 kv_set_valid_clock_range(rdev, new_ps);
1886 kv_update_dfs_bypass_settings(rdev, new_ps);
1887 ret = kv_calculate_ds_divider(rdev);
1892 kv_calculate_nbps_level_settings(rdev);
1893 kv_calculate_dpm_settings(rdev);
1894 kv_freeze_sclk_dpm(rdev, true);
1895 kv_upload_dpm_settings(rdev);
1896 kv_program_nbps_index_settings(rdev, new_ps);
1897 kv_freeze_sclk_dpm(rdev, false);
1898 kv_set_enabled_levels(rdev);
1899 ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1904 kv_update_acp_boot_level(rdev);
1905 kv_update_sclk_t(rdev);
1906 kv_enable_nb_dpm(rdev, true);
1913 void kv_dpm_post_set_power_state(struct radeon_device *rdev)
1915 struct kv_power_info *pi = kv_get_pi(rdev);
1918 kv_update_current_ps(rdev, new_ps);
1921 void kv_dpm_setup_asic(struct radeon_device *rdev)
1923 sumo_take_smu_control(rdev, true);
1924 kv_init_powergate_state(rdev);
1925 kv_init_sclk_t(rdev);
1928 void kv_dpm_reset_asic(struct radeon_device *rdev)
1930 struct kv_power_info *pi = kv_get_pi(rdev);
1932 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
1933 kv_force_lowest_valid(rdev);
1934 kv_init_graphics_levels(rdev);
1935 kv_program_bootup_state(rdev);
1936 kv_upload_dpm_settings(rdev);
1937 kv_force_lowest_valid(rdev);
1938 kv_unforce_levels(rdev);
1940 kv_init_graphics_levels(rdev);
1941 kv_program_bootup_state(rdev);
1942 kv_freeze_sclk_dpm(rdev, true);
1943 kv_upload_dpm_settings(rdev);
1944 kv_freeze_sclk_dpm(rdev, false);
1945 kv_set_enabled_level(rdev, pi->graphics_boot_level);
1951 static void kv_construct_max_power_limits_table(struct radeon_device *rdev,
1954 struct kv_power_info *pi = kv_get_pi(rdev);
1961 kv_convert_2bit_index_to_voltage(rdev,
1968 static void kv_patch_voltage_values(struct radeon_device *rdev)
1972 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1974 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1976 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1978 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1983 kv_convert_8bit_index_to_voltage(rdev,
1990 kv_convert_8bit_index_to_voltage(rdev,
1997 kv_convert_8bit_index_to_voltage(rdev,
2004 kv_convert_8bit_index_to_voltage(rdev,
2010 static void kv_construct_boot_state(struct radeon_device *rdev)
2012 struct kv_power_info *pi = kv_get_pi(rdev);
2024 static int kv_force_dpm_highest(struct radeon_device *rdev)
2029 ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
2038 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
2039 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
2041 return kv_set_enabled_level(rdev, i);
2044 static int kv_force_dpm_lowest(struct radeon_device *rdev)
2049 ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
2058 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
2059 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
2061 return kv_set_enabled_level(rdev, i);
2064 static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2067 struct kv_power_info *pi = kv_get_pi(rdev);
2088 static int kv_get_high_voltage_limit(struct radeon_device *rdev, int *limit)
2090 struct kv_power_info *pi = kv_get_pi(rdev);
2092 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2098 (kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v) <=
2110 (kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit) <=
2122 static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
2127 struct kv_power_info *pi = kv_get_pi(rdev);
2133 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2136 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2139 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
2140 new_rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
2166 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
2167 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
2181 kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
2182 kv_get_high_voltage_limit(rdev, &limit);
2193 kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
2194 kv_get_high_voltage_limit(rdev, &limit);
2215 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
2228 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) ||
2238 static void kv_dpm_power_level_enabled_for_throttle(struct radeon_device *rdev,
2241 struct kv_power_info *pi = kv_get_pi(rdev);
2246 static int kv_calculate_ds_divider(struct radeon_device *rdev)
2248 struct kv_power_info *pi = kv_get_pi(rdev);
2257 kv_get_sleep_divider_id_from_clock(rdev,
2264 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev)
2266 struct kv_power_info *pi = kv_get_pi(rdev);
2270 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2276 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
2287 (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
2318 static int kv_calculate_dpm_settings(struct radeon_device *rdev)
2320 struct kv_power_info *pi = kv_get_pi(rdev);
2332 static void kv_init_graphics_levels(struct radeon_device *rdev)
2334 struct kv_power_info *pi = kv_get_pi(rdev);
2337 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2346 kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v)))
2349 kv_set_divider_value(rdev, i, table->entries[i].clk);
2350 vid_2bit = kv_convert_vid7_to_vid2(rdev,
2353 kv_set_vid(rdev, i, vid_2bit);
2354 kv_set_at(rdev, i, pi->at[i]);
2355 kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2366 kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit))
2369 kv_set_divider_value(rdev, i, table->entries[i].sclk_frequency);
2370 kv_set_vid(rdev, i, table->entries[i].vid_2bit);
2371 kv_set_at(rdev, i, pi->at[i]);
2372 kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2378 kv_dpm_power_level_enable(rdev, i, false);
2381 static void kv_enable_new_levels(struct radeon_device *rdev)
2383 struct kv_power_info *pi = kv_get_pi(rdev);
2388 kv_dpm_power_level_enable(rdev, i, true);
2392 static int kv_set_enabled_level(struct radeon_device *rdev, u32 level)
2396 return kv_send_msg_to_smc_with_parameter(rdev,
2401 static int kv_set_enabled_levels(struct radeon_device *rdev)
2403 struct kv_power_info *pi = kv_get_pi(rdev);
2409 return kv_send_msg_to_smc_with_parameter(rdev,
2414 static void kv_program_nbps_index_settings(struct radeon_device *rdev,
2418 struct kv_power_info *pi = kv_get_pi(rdev);
2421 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
2436 static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
2458 rdev->pm.dpm.thermal.min_temp = low_temp;
2459 rdev->pm.dpm.thermal.max_temp = high_temp;
2473 static int kv_parse_sys_info_table(struct radeon_device *rdev)
2475 struct kv_power_info *pi = kv_get_pi(rdev);
2476 struct radeon_mode_info *mode_info = &rdev->mode_info;
2523 sumo_construct_sclk_voltage_mapping_table(rdev,
2527 sumo_construct_vid_mapping_table(rdev,
2531 kv_construct_max_power_limits_table(rdev,
2532 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
2558 static void kv_patch_boot_state(struct radeon_device *rdev,
2561 struct kv_power_info *pi = kv_get_pi(rdev);
2567 static void kv_parse_pplib_non_clock_info(struct radeon_device *rdev,
2587 rdev->pm.dpm.boot_ps = rps;
2588 kv_patch_boot_state(rdev, ps);
2591 rdev->pm.dpm.uvd_ps = rps;
2594 static void kv_parse_pplib_clock_info(struct radeon_device *rdev,
2598 struct kv_power_info *pi = kv_get_pi(rdev);
2616 static int kv_parse_power_table(struct radeon_device *rdev)
2618 struct radeon_mode_info *mode_info = &rdev->mode_info;
2648 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
2650 if (!rdev->pm.dpm.ps)
2659 if (!rdev->pm.power_state[i].clock_info)
2663 kfree(rdev->pm.dpm.ps);
2666 rdev->pm.dpm.ps[i].ps_priv = ps;
2678 kv_parse_pplib_clock_info(rdev,
2679 &rdev->pm.dpm.ps[i], k,
2683 kv_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
2688 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
2693 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
2698 rdev->pm.dpm.vce_states[i].sclk = sclk;
2699 rdev->pm.dpm.vce_states[i].mclk = 0;
2705 int kv_dpm_init(struct radeon_device *rdev)
2713 rdev->pm.dpm.priv = pi;
2715 ret = r600_get_platform_caps(rdev);
2719 ret = r600_parse_extended_power_table(rdev);
2729 if (rdev->pdev->subsystem_vendor == 0x1849)
2751 if (rdev->pdev->subsystem_vendor == 0x1849)
2770 ret = kv_parse_sys_info_table(rdev);
2774 kv_patch_voltage_values(rdev);
2775 kv_construct_boot_state(rdev);
2777 ret = kv_parse_power_table(rdev);
2786 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2789 struct kv_power_info *pi = kv_get_pi(rdev);
2802 vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp);
2810 void kv_dpm_print_power_state(struct radeon_device *rdev,
2823 kv_convert_8bit_index_to_voltage(rdev, pl->vddc_index));
2825 r600_dpm_print_ps_status(rdev, rps);
2828 void kv_dpm_fini(struct radeon_device *rdev)
2832 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2833 kfree(rdev->pm.dpm.ps[i].ps_priv);
2835 kfree(rdev->pm.dpm.ps);
2836 kfree(rdev->pm.dpm.priv);
2837 r600_free_extended_power_table(rdev);
2840 void kv_dpm_display_configuration_changed(struct radeon_device *rdev)
2845 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low)
2847 struct kv_power_info *pi = kv_get_pi(rdev);
2856 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low)
2858 struct kv_power_info *pi = kv_get_pi(rdev);