Cross Reference: /drivers/gpu/drm/radeon/ni

Lines Matching defs:pl
1614 						struct rv7xx_pl *pl,
1621 		(u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk);
1625                                             pl->sclk,
1626                                             pl->mclk);
2310 					 struct rv7xx_pl *pl,
2322 		((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;
2324 	ret = ni_populate_sclk_value(rdev, pl->sclk, &level->sclk);
2330 	    (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
2337 		if (pl->mclk > pi->mclk_edc_enable_threshold)
2339 		if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
2342 		level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);
2345 			if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=
2352 			if (pl->mclk > ni_pi->mclk_rtt_mode_threshold)
2356 		ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk,
2361 		ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk, &level->mclk, 1, 1);
2367 					pl->vddc, &level->vddc);
2380 						pl->vddci, &level->vddci);
2385 	ni_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
2958 						 struct rv7xx_pl *pl,
2965 		if (pl->mclk <= ni_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
3925 	struct rv7xx_pl *pl = &ps->performance_levels[index];
3929 	pl->sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
3930 	pl->sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
3931 	pl->mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
3932 	pl->mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
3934 	pl->vddc = le16_to_cpu(clock_info->evergreen.usVDDC);
3935 	pl->vddci = le16_to_cpu(clock_info->evergreen.usVDDCI);
3936 	pl->flags = le32_to_cpu(clock_info->evergreen.ulFlags);
3939 	if (pl->vddc == 0xff01) {
3941 			pl->vddc = pi->max_vddc;
3945 		pi->acpi_vddc = pl->vddc;
3946 		eg_pi->acpi_vddci = pl->vddci;
3955 		eg_pi->ulv.pl = pl;
3958 	if (pi->min_vddc_in_table > pl->vddc)
3959 		pi->min_vddc_in_table = pl->vddc;
3961 	if (pi->max_vddc_in_table < pl->vddc)
3962 		pi->max_vddc_in_table = pl->vddc;
3968 		pl->mclk = rdev->clock.default_mclk;
3969 		pl->sclk = rdev->clock.default_sclk;
3970 		pl->vddc = vddc;
3971 		pl->vddci = vddci;
3976 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
3977 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
3978 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
3979 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
4281 	struct rv7xx_pl *pl;
4288 		pl = &ps->performance_levels[i];
4291 			       i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
4294 			       i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
4305 	struct rv7xx_pl *pl;
4313 		pl = &ps->performance_levels[current_index];
4316 			   current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci);