Lines Matching refs:dst_offset
2480 u64 src_offset, dst_offset;
2503 dst_offset = radeon_get_ib_value(p, idx+1);
2504 dst_offset <<= 8;
2509 dst_offset = radeon_get_ib_value(p, idx+1);
2510 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2516 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2518 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2542 dst_offset = radeon_get_ib_value(p, idx+5);
2543 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
2553 dst_offset = radeon_get_ib_value(p, idx+1);
2554 dst_offset <<= 8;
2562 dst_offset = radeon_get_ib_value(p, idx+1);
2563 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
2573 dst_offset = radeon_get_ib_value(p, idx+1);
2574 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;
2588 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2590 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2604 dst_offset = radeon_get_ib_value(p, idx+1);
2605 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;
2606 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2608 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));