Lines Matching refs:rdev
48 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
53 if ((rdev->family == CHIP_R420) ||
54 (rdev->family == CHIP_R423) ||
55 (rdev->family == CHIP_RV410)) {
65 if (ASIC_IS_DCE4(rdev)) {
78 if (ASIC_IS_DCE3(rdev)) {
129 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
132 struct atom_context *ctx = rdev->mode_info.atom_context;
152 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
166 void radeon_atombios_i2c_init(struct radeon_device *rdev)
168 struct atom_context *ctx = rdev->mode_info.atom_context;
185 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
191 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
199 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
202 struct atom_context *ctx = rdev->mode_info.atom_context;
236 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
244 if (ASIC_IS_DCE6(rdev))
246 else if (ASIC_IS_DCE4(rdev))
434 struct radeon_device *rdev = dev->dev_private;
435 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
524 struct radeon_device *rdev = dev->dev_private;
525 struct radeon_mode_info *mode_info = &rdev->mode_info;
591 if ((rdev->flags & RADEON_IS_IGP) &&
734 radeon_lookup_i2c_gpio(rdev,
796 ddc_bus = radeon_lookup_i2c_gpio(rdev,
804 gpio = radeon_lookup_gpio(rdev,
806 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
854 struct radeon_device *rdev = dev->dev_private;
856 if (rdev->flags & RADEON_IS_IGP) {
862 struct radeon_mode_info *mode_info = &rdev->mode_info;
905 struct radeon_device *rdev = dev->dev_private;
906 struct radeon_mode_info *mode_info = &rdev->mode_info;
983 radeon_lookup_i2c_gpio(rdev,
1025 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1115 struct radeon_device *rdev = dev->dev_private;
1116 struct radeon_mode_info *mode_info = &rdev->mode_info;
1120 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1121 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1122 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1123 struct radeon_pll *spll = &rdev->clock.spll;
1124 struct radeon_pll *mpll = &rdev->clock.mpll;
1161 if (ASIC_IS_AVIVO(rdev))
1175 if (ASIC_IS_DCE4(rdev))
1190 if (ASIC_IS_AVIVO(rdev))
1202 if (ASIC_IS_DCE4(rdev))
1217 if (ASIC_IS_AVIVO(rdev))
1228 rdev->clock.default_sclk =
1230 rdev->clock.default_mclk =
1233 if (ASIC_IS_DCE4(rdev)) {
1234 rdev->clock.default_dispclk =
1236 if (rdev->clock.default_dispclk == 0) {
1237 if (ASIC_IS_DCE6(rdev))
1238 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1239 else if (ASIC_IS_DCE5(rdev))
1240 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1242 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1245 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1247 rdev->clock.default_dispclk / 100);
1248 rdev->clock.default_dispclk = 60000;
1250 rdev->clock.dp_extclk =
1252 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1256 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1257 if (rdev->clock.max_pixel_clock == 0)
1258 rdev->clock.max_pixel_clock = 40000;
1261 rdev->mode_info.firmware_flags =
1278 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1280 struct radeon_mode_info *mode_info = &rdev->mode_info;
1287 if (rdev->family == CHIP_RS600)
1315 struct radeon_device *rdev = dev->dev_private;
1316 struct radeon_mode_info *mode_info = &rdev->mode_info;
1360 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1364 struct radeon_mode_info *mode_info = &rdev->mode_info;
1400 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1404 struct radeon_mode_info *mode_info = &rdev->mode_info;
1488 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1492 struct radeon_mode_info *mode_info = &rdev->mode_info;
1501 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1505 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1577 if (rdev->flags & RADEON_IS_IGP)
1578 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1604 struct radeon_device *rdev = dev->dev_private;
1605 struct radeon_mode_info *mode_info = &rdev->mode_info;
1711 rdev->mode_info.bios_hardcoded_edid = edid;
1712 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1744 struct radeon_device *rdev = dev->dev_private;
1745 struct radeon_mode_info *mode_info = &rdev->mode_info;
1771 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1774 struct radeon_mode_info *mode_info = &rdev->mode_info;
1869 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1871 struct radeon_mode_info *mode_info = &rdev->mode_info;
1930 struct radeon_device *rdev = dev->dev_private;
1931 struct radeon_mode_info *mode_info = &rdev->mode_info;
1962 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
2023 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2027 rdev->pm.power_state[state_index].misc = misc;
2028 rdev->pm.power_state[state_index].misc2 = misc2;
2031 rdev->pm.power_state[state_index].type =
2034 rdev->pm.power_state[state_index].type =
2037 rdev->pm.power_state[state_index].type =
2040 rdev->pm.power_state[state_index].type =
2043 rdev->pm.power_state[state_index].type =
2045 rdev->pm.power_state[state_index].flags &=
2049 rdev->pm.power_state[state_index].type =
2052 rdev->pm.power_state[state_index].type =
2054 rdev->pm.default_power_state_index = state_index;
2055 rdev->pm.power_state[state_index].default_clock_mode =
2056 &rdev->pm.power_state[state_index].clock_info[0];
2058 rdev->pm.power_state[state_index].clock_info[0].flags |=
2063 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2065 struct radeon_mode_info *mode_info = &rdev->mode_info;
2086 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2087 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2088 if (rdev->pm.i2c_bus) {
2094 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2102 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2103 if (!rdev->pm.power_state)
2107 rdev->pm.power_state[state_index].clock_info =
2109 if (!rdev->pm.power_state[state_index].clock_info)
2111 rdev->pm.power_state[state_index].num_clock_modes = 1;
2112 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2115 rdev->pm.power_state[state_index].clock_info[0].mclk =
2117 rdev->pm.power_state[state_index].clock_info[0].sclk =
2120 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2121 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2123 rdev->pm.power_state[state_index].pcie_lanes =
2128 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2130 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2131 radeon_lookup_gpio(rdev,
2134 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2137 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2140 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2142 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2145 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2146 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2150 rdev->pm.power_state[state_index].clock_info[0].mclk =
2152 rdev->pm.power_state[state_index].clock_info[0].sclk =
2155 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2156 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2158 rdev->pm.power_state[state_index].pcie_lanes =
2164 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2166 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2167 radeon_lookup_gpio(rdev,
2170 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2173 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2176 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2178 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2181 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2182 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2186 rdev->pm.power_state[state_index].clock_info[0].mclk =
2188 rdev->pm.power_state[state_index].clock_info[0].sclk =
2191 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2192 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2194 rdev->pm.power_state[state_index].pcie_lanes =
2200 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2202 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2203 radeon_lookup_gpio(rdev,
2206 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2209 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2212 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2214 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2217 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2219 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2223 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2224 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2230 if (rdev->pm.default_power_state_index == -1) {
2231 rdev->pm.power_state[state_index - 1].type =
2233 rdev->pm.default_power_state_index = state_index - 1;
2234 rdev->pm.power_state[state_index - 1].default_clock_mode =
2235 &rdev->pm.power_state[state_index - 1].clock_info[0];
2236 rdev->pm.power_state[state_index].flags &=
2238 rdev->pm.power_state[state_index].misc = 0;
2239 rdev->pm.power_state[state_index].misc2 = 0;
2244 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2255 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2260 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2265 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2270 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2275 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2280 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2285 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2290 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2296 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2302 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2308 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2315 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2316 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2317 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2318 if (rdev->pm.i2c_bus) {
2323 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2335 void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2338 struct radeon_mode_info *mode_info = &rdev->mode_info;
2361 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2370 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2372 rdev->pm.power_state[state_index].misc = misc;
2373 rdev->pm.power_state[state_index].misc2 = misc2;
2374 rdev->pm.power_state[state_index].pcie_lanes =
2379 rdev->pm.power_state[state_index].type =
2383 rdev->pm.power_state[state_index].type =
2387 rdev->pm.power_state[state_index].type =
2392 rdev->pm.power_state[state_index].type =
2396 rdev->pm.power_state[state_index].flags = 0;
2398 rdev->pm.power_state[state_index].flags |=
2401 rdev->pm.power_state[state_index].type =
2403 rdev->pm.default_power_state_index = state_index;
2404 rdev->pm.power_state[state_index].default_clock_mode =
2405 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2406 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2408 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2409 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2410 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2411 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2415 if (ASIC_IS_DCE4(rdev))
2416 radeon_atom_get_max_voltage(rdev,
2421 rdev->pm.power_state[state_index].clock_info[j].mclk =
2422 rdev->clock.default_mclk;
2423 rdev->pm.power_state[state_index].clock_info[j].sclk =
2424 rdev->clock.default_sclk;
2426 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2429 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2436 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2443 if (rdev->flags & RADEON_IS_IGP) {
2444 if (rdev->family >= CHIP_PALM) {
2447 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2451 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2453 } else if (rdev->family >= CHIP_BONAIRE) {
2458 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2459 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2460 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2462 } else if (rdev->family >= CHIP_TAHITI) {
2467 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2468 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2469 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2471 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2473 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2475 } else if (rdev->family >= CHIP_CEDAR) {
2480 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2481 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2482 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2484 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2486 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2493 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2494 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2495 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2497 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2502 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2511 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2512 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2514 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2520 if (rdev->flags & RADEON_IS_IGP) {
2522 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2526 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2527 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2533 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2535 struct radeon_mode_info *mode_info = &rdev->mode_info;
2552 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2555 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2557 if (!rdev->pm.power_state)
2571 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2575 if (!rdev->pm.power_state[i].clock_info)
2584 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2591 rdev->pm.power_state[state_index].clock_info[0].mclk =
2592 rdev->clock.default_mclk;
2593 rdev->pm.power_state[state_index].clock_info[0].sclk =
2594 rdev->clock.default_sclk;
2597 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2599 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2606 if (rdev->pm.power_state[i].num_clock_modes > 1)
2607 rdev->pm.power_state[i].clock_info[0].flags |=
2611 if (rdev->pm.default_power_state_index == -1) {
2612 rdev->pm.power_state[0].type =
2614 rdev->pm.default_power_state_index = 0;
2615 rdev->pm.power_state[0].default_clock_mode =
2616 &rdev->pm.power_state[0].clock_info[0];
2621 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2623 struct radeon_mode_info *mode_info = &rdev->mode_info;
2644 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2656 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2658 if (!rdev->pm.power_state)
2667 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2671 if (!rdev->pm.power_state[i].clock_info)
2678 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2685 rdev->pm.power_state[state_index].clock_info[0].mclk =
2686 rdev->clock.default_mclk;
2687 rdev->pm.power_state[state_index].clock_info[0].sclk =
2688 rdev->clock.default_sclk;
2691 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2693 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2701 if (rdev->pm.power_state[i].num_clock_modes > 1)
2702 rdev->pm.power_state[i].clock_info[0].flags |=
2706 if (rdev->pm.default_power_state_index == -1) {
2707 rdev->pm.power_state[0].type =
2709 rdev->pm.default_power_state_index = 0;
2710 rdev->pm.power_state[0].default_clock_mode =
2711 &rdev->pm.power_state[0].clock_info[0];
2716 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2718 struct radeon_mode_info *mode_info = &rdev->mode_info;
2724 rdev->pm.default_power_state_index = -1;
2732 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2736 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2739 state_index = radeon_atombios_parse_power_table_6(rdev);
2747 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2748 if (rdev->pm.power_state) {
2749 rdev->pm.power_state[0].clock_info =
2751 if (rdev->pm.power_state[0].clock_info) {
2753 rdev->pm.power_state[state_index].type =
2755 rdev->pm.power_state[state_index].num_clock_modes = 1;
2756 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2757 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2758 rdev->pm.power_state[state_index].default_clock_mode =
2759 &rdev->pm.power_state[state_index].clock_info[0];
2760 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2761 rdev->pm.power_state[state_index].pcie_lanes = 16;
2762 rdev->pm.default_power_state_index = state_index;
2763 rdev->pm.power_state[state_index].flags = 0;
2769 rdev->pm.num_power_states = state_index;
2771 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2772 rdev->pm.current_clock_mode_index = 0;
2773 if (rdev->pm.default_power_state_index >= 0)
2774 rdev->pm.current_vddc =
2775 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2777 rdev->pm.current_vddc = 0;
2790 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2803 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2812 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2822 if (rdev->family <= CHIP_RV770) {
2826 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2831 if (rdev->family == CHIP_RV770) {
2841 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2855 if (rdev->family >= CHIP_TAHITI)
2861 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2880 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2891 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2907 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2919 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2932 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2958 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2965 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2968 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2973 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2977 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2982 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2986 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2994 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2997 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3003 if (rdev->flags & RADEON_IS_IGP)
3008 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3011 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3027 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3030 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3038 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3041 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3050 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3060 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3066 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3094 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3097 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3104 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3115 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3124 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3136 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3140 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3143 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3150 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3160 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3172 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3187 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3192 (rdev->mode_info.atom_context->bios + data_offset);
3203 (rdev->mode_info.atom_context->bios + data_offset +
3206 (rdev->mode_info.atom_context->bios + data_offset +
3209 (rdev->mode_info.atom_context->bios + data_offset +
3212 (rdev->mode_info.atom_context->bios + data_offset +
3215 (rdev->mode_info.atom_context->bios + data_offset +
3263 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3269 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3273 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3284 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3286 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3293 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3301 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3312 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3320 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3396 radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3405 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3408 (rdev->mode_info.atom_context->bios + data_offset);
3454 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3464 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3467 (rdev->mode_info.atom_context->bios + data_offset);
3498 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3507 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3510 (rdev->mode_info.atom_context->bios + data_offset);
3557 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3566 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3569 (rdev->mode_info.atom_context->bios + data_offset);
3607 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3616 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3619 (rdev->mode_info.atom_context->bios + data_offset);
3648 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3655 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3657 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3659 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3674 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3685 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3688 (rdev->mode_info.atom_context->bios + data_offset);
3710 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3775 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3785 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3788 (rdev->mode_info.atom_context->bios + data_offset);
3864 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3877 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3880 (rdev->mode_info.atom_context->bios + data_offset);
3937 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3949 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3952 (rdev->mode_info.atom_context->bios + data_offset);
4030 struct radeon_device *rdev = dev->dev_private;
4033 if (rdev->family >= CHIP_R600) {
4048 if (ASIC_IS_DCE4(rdev))
4051 if (rdev->family >= CHIP_R600) {
4061 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4066 if (rdev->family >= CHIP_R600)
4072 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4075 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4080 if (rdev->family >= CHIP_R600)
4086 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4092 struct radeon_device *rdev = dev->dev_private;
4095 if (rdev->family >= CHIP_R600)
4108 if (rdev->family >= CHIP_R600)
4121 struct radeon_device *rdev = dev->dev_private;
4127 if (rdev->family >= CHIP_R600) {
4290 if (rdev->family >= CHIP_R600) {
4305 struct radeon_device *rdev = dev->dev_private;
4309 if (ASIC_IS_DCE4(rdev))
4312 if (rdev->family >= CHIP_R600)
4350 if (rdev->family >= CHIP_R600)
4360 struct radeon_device *rdev = dev->dev_private;
4364 if (ASIC_IS_DCE4(rdev))
4367 if (rdev->family >= CHIP_R600)
4433 if (rdev->family >= CHIP_R600)