Cross Reference: /drivers/gpu/drm/radeon/radeon

Lines Matching defs:sarea_priv
774 	x += master_priv->sarea_priv->boxes[0].x1;
775 	y += master_priv->sarea_priv->boxes[0].y1;
803 	if (master_priv->sarea_priv->pfCurrentPage == 1) {
881 	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
883 	int nbox = sarea_priv->nbox;
884 	struct drm_clip_rect *pbox = sarea_priv->boxes;
893 	if (sarea_priv->pfCurrentPage == 1) {
925 		sarea_priv->ctx_owner = 0;
1002 		sarea_priv->ctx_owner = 0;
1249 		sarea_priv->ctx_owner = 0;
1256 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1320 		sarea_priv->ctx_owner = 0;
1327 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1363 	sarea_priv->last_clear++;
1367 	RADEON_CLEAR_AGE(sarea_priv->last_clear);
1377 	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
1378 	int nbox = sarea_priv->nbox;
1379 	struct drm_clip_rect *pbox = sarea_priv->boxes;
1421 		if (sarea_priv->pfCurrentPage == 0) {
1441 	sarea_priv->last_frame++;
1445 	RADEON_FRAME_AGE(sarea_priv->last_frame);
1456 	int offset = (master_priv->sarea_priv->pfCurrentPage == 1)
1460 		  master_priv->sarea_priv->pfCurrentPage);
1478 	OUT_RING_REG(RADEON_CRTC2_OFFSET, master_priv->sarea_priv->crtc2_base
1487 	master_priv->sarea_priv->last_frame++;
1488 	master_priv->sarea_priv->pfCurrentPage =
1489 		1 - master_priv->sarea_priv->pfCurrentPage;
1493 	RADEON_FRAME_AGE(master_priv->sarea_priv->last_frame);
1537 	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
1540 	int nbox = sarea_priv->nbox;
1557 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1585 	buf_priv->age = ++master_priv->sarea_priv->last_dispatch;
1643 	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
1650 	int nbox = sarea_priv->nbox;
1684 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
2159 	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
2168 	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2169 		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2172 			       sarea_priv->nbox * sizeof(depth_boxes[0])))
2203 	if (master_priv->sarea_priv->pfCurrentPage != 1)
2204 		master_priv->sarea_priv->pfCurrentPage = 0;
2234 	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
2242 	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2243 		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2249 	sarea_priv->ctx_owner = 0;
2259 	drm_radeon_sarea_t *sarea_priv;
2267 	sarea_priv = master_priv->sarea_priv;
2302 		if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2304 					      &sarea_priv->context_state,
2305 					      sarea_priv->tex_state,
2306 					      sarea_priv->dirty)) {
2311 			sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2321 		prim.vc_format = sarea_priv->vc_format;
2338 	drm_radeon_sarea_t *sarea_priv;
2347 	sarea_priv = master_priv->sarea_priv;
2392 	if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2394 				      &sarea_priv->context_state,
2395 				      sarea_priv->tex_state,
2396 				      sarea_priv->dirty)) {
2401 		sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2414 	prim.vc_format = sarea_priv->vc_format;
2545 	drm_radeon_sarea_t *sarea_priv;
2554 	sarea_priv = master_priv->sarea_priv;
2581 	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2624 		if (sarea_priv->nbox == 1)
2625 			sarea_priv->nbox = 0;
3145 			if (master_priv->sarea_priv)
3146 				master_priv->sarea_priv->tiling_enabled = 0;
3151 			if (master_priv->sarea_priv)
3152 				master_priv->sarea_priv->tiling_enabled = 1;