Lines Matching defs:rdev
41 static void rv770_gpu_init(struct radeon_device *rdev);
42 void rv770_fini(struct radeon_device *rdev);
43 static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
44 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
46 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
52 if (rdev->family == CHIP_RV740)
53 return evergreen_set_uvd_clocks(rdev, vclk, dclk);
66 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
86 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
117 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
715 static void rv770_init_golden_registers(struct radeon_device *rdev)
717 switch (rdev->family) {
719 radeon_program_register_sequence(rdev,
722 radeon_program_register_sequence(rdev,
725 if (rdev->pdev->device == 0x994e)
726 radeon_program_register_sequence(rdev,
730 radeon_program_register_sequence(rdev,
733 radeon_program_register_sequence(rdev,
738 radeon_program_register_sequence(rdev,
741 radeon_program_register_sequence(rdev,
744 radeon_program_register_sequence(rdev,
747 radeon_program_register_sequence(rdev,
752 radeon_program_register_sequence(rdev,
755 radeon_program_register_sequence(rdev,
758 radeon_program_register_sequence(rdev,
761 radeon_program_register_sequence(rdev,
766 radeon_program_register_sequence(rdev,
769 radeon_program_register_sequence(rdev,
784 * @rdev: radeon_device pointer
789 u32 rv770_get_xclk(struct radeon_device *rdev)
791 u32 reference_clock = rdev->clock.spll.reference_freq;
803 void rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
805 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
827 for (i = 0; i < rdev->usec_timeout; i++) {
839 bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc_id)
841 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
849 int rv770_get_temp(struct radeon_device *rdev)
868 void rv770_pm_misc(struct radeon_device *rdev)
870 int req_ps_idx = rdev->pm.requested_power_state_index;
871 int req_cm_idx = rdev->pm.requested_clock_mode_index;
872 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
879 if (voltage->voltage != rdev->pm.current_vddc) {
880 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
881 rdev->pm.current_vddc = voltage->voltage;
890 static int rv770_pcie_gart_enable(struct radeon_device *rdev)
895 if (rdev->gart.robj == NULL) {
896 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
899 r = radeon_gart_table_vram_pin(rdev);
916 if (rdev->family == CHIP_RV740)
922 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
923 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
924 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
928 (u32)(rdev->dummy_page.addr >> 12));
932 r600_pcie_gart_tlb_flush(rdev);
934 (unsigned)(rdev->mc.gtt_size >> 20),
935 (unsigned long long)rdev->gart.table_addr);
936 rdev->gart.ready = true;
940 static void rv770_pcie_gart_disable(struct radeon_device *rdev)
963 radeon_gart_table_vram_unpin(rdev);
966 static void rv770_pcie_gart_fini(struct radeon_device *rdev)
968 radeon_gart_fini(rdev);
969 rv770_pcie_gart_disable(rdev);
970 radeon_gart_table_vram_free(rdev);
974 static void rv770_agp_enable(struct radeon_device *rdev)
1001 static void rv770_mc_program(struct radeon_device *rdev)
1020 rv515_mc_stop(rdev, &save);
1021 if (r600_mc_wait_for_idle(rdev)) {
1022 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1027 if (rdev->flags & RADEON_IS_AGP) {
1028 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1031 rdev->mc.vram_start >> 12);
1033 rdev->mc.gtt_end >> 12);
1037 rdev->mc.gtt_start >> 12);
1039 rdev->mc.vram_end >> 12);
1043 rdev->mc.vram_start >> 12);
1045 rdev->mc.vram_end >> 12);
1047 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1048 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1049 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1051 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1054 if (rdev->flags & RADEON_IS_AGP) {
1055 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1056 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1057 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1063 if (r600_mc_wait_for_idle(rdev)) {
1064 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1066 rv515_mc_resume(rdev, &save);
1069 rv515_vga_render_disable(rdev);
1076 void r700_cp_stop(struct radeon_device *rdev)
1078 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1079 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1082 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1085 static int rv770_cp_load_microcode(struct radeon_device *rdev)
1090 if (!rdev->me_fw || !rdev->pfp_fw)
1093 r700_cp_stop(rdev);
1106 fw_data = (const __be32 *)rdev->pfp_fw->data;
1112 fw_data = (const __be32 *)rdev->me_fw->data;
1123 void r700_cp_fini(struct radeon_device *rdev)
1125 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1126 r700_cp_stop(rdev);
1127 radeon_ring_fini(rdev, ring);
1128 radeon_scratch_free(rdev, ring->rptr_save_reg);
1131 void rv770_set_clk_bypass_mode(struct radeon_device *rdev)
1135 if (rdev->flags & RADEON_IS_IGP)
1143 for (i = 0; i < rdev->usec_timeout; i++) {
1153 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1163 static void rv770_gpu_init(struct radeon_device *rdev)
1187 rdev->config.rv770.tiling_group_size = 256;
1188 switch (rdev->family) {
1190 rdev->config.rv770.max_pipes = 4;
1191 rdev->config.rv770.max_tile_pipes = 8;
1192 rdev->config.rv770.max_simds = 10;
1193 rdev->config.rv770.max_backends = 4;
1194 rdev->config.rv770.max_gprs = 256;
1195 rdev->config.rv770.max_threads = 248;
1196 rdev->config.rv770.max_stack_entries = 512;
1197 rdev->config.rv770.max_hw_contexts = 8;
1198 rdev->config.rv770.max_gs_threads = 16 * 2;
1199 rdev->config.rv770.sx_max_export_size = 128;
1200 rdev->config.rv770.sx_max_export_pos_size = 16;
1201 rdev->config.rv770.sx_max_export_smx_size = 112;
1202 rdev->config.rv770.sq_num_cf_insts = 2;
1204 rdev->config.rv770.sx_num_of_sets = 7;
1205 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
1206 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1207 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1210 rdev->config.rv770.max_pipes = 2;
1211 rdev->config.rv770.max_tile_pipes = 4;
1212 rdev->config.rv770.max_simds = 8;
1213 rdev->config.rv770.max_backends = 2;
1214 rdev->config.rv770.max_gprs = 128;
1215 rdev->config.rv770.max_threads = 248;
1216 rdev->config.rv770.max_stack_entries = 256;
1217 rdev->config.rv770.max_hw_contexts = 8;
1218 rdev->config.rv770.max_gs_threads = 16 * 2;
1219 rdev->config.rv770.sx_max_export_size = 256;
1220 rdev->config.rv770.sx_max_export_pos_size = 32;
1221 rdev->config.rv770.sx_max_export_smx_size = 224;
1222 rdev->config.rv770.sq_num_cf_insts = 2;
1224 rdev->config.rv770.sx_num_of_sets = 7;
1225 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
1226 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1227 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1228 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
1229 rdev->config.rv770.sx_max_export_pos_size -= 16;
1230 rdev->config.rv770.sx_max_export_smx_size += 16;
1234 rdev->config.rv770.max_pipes = 2;
1235 rdev->config.rv770.max_tile_pipes = 2;
1236 rdev->config.rv770.max_simds = 2;
1237 rdev->config.rv770.max_backends = 1;
1238 rdev->config.rv770.max_gprs = 256;
1239 rdev->config.rv770.max_threads = 192;
1240 rdev->config.rv770.max_stack_entries = 256;
1241 rdev->config.rv770.max_hw_contexts = 4;
1242 rdev->config.rv770.max_gs_threads = 8 * 2;
1243 rdev->config.rv770.sx_max_export_size = 128;
1244 rdev->config.rv770.sx_max_export_pos_size = 16;
1245 rdev->config.rv770.sx_max_export_smx_size = 112;
1246 rdev->config.rv770.sq_num_cf_insts = 1;
1248 rdev->config.rv770.sx_num_of_sets = 7;
1249 rdev->config.rv770.sc_prim_fifo_size = 0x40;
1250 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1251 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1254 rdev->config.rv770.max_pipes = 4;
1255 rdev->config.rv770.max_tile_pipes = 4;
1256 rdev->config.rv770.max_simds = 8;
1257 rdev->config.rv770.max_backends = 4;
1258 rdev->config.rv770.max_gprs = 256;
1259 rdev->config.rv770.max_threads = 248;
1260 rdev->config.rv770.max_stack_entries = 512;
1261 rdev->config.rv770.max_hw_contexts = 8;
1262 rdev->config.rv770.max_gs_threads = 16 * 2;
1263 rdev->config.rv770.sx_max_export_size = 256;
1264 rdev->config.rv770.sx_max_export_pos_size = 32;
1265 rdev->config.rv770.sx_max_export_smx_size = 224;
1266 rdev->config.rv770.sq_num_cf_insts = 2;
1268 rdev->config.rv770.sx_num_of_sets = 7;
1269 rdev->config.rv770.sc_prim_fifo_size = 0x100;
1270 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1271 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1273 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
1274 rdev->config.rv770.sx_max_export_pos_size -= 16;
1275 rdev->config.rv770.sx_max_export_smx_size += 16;
1313 tmp = rdev->config.rv770.max_simds -
1315 rdev->config.rv770.active_simds = tmp;
1317 switch (rdev->config.rv770.max_tile_pipes) {
1332 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
1336 for (i = 0; i < rdev->config.rv770.max_backends; i++)
1340 for (i = 0; i < rdev->config.rv770.max_backends; i++)
1344 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
1347 rdev->config.rv770.backend_map = tmp;
1349 if (rdev->family == CHIP_RV770)
1357 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
1370 rdev->config.rv770.tile_config = gb_tiling_config;
1377 if (rdev->family == CHIP_RV730) {
1408 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
1411 if (rdev->family != CHIP_RV740)
1417 if (rdev->family != CHIP_RV770)
1422 switch (rdev->family) {
1435 if (rdev->family != CHIP_RV770) {
1441 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
1442 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
1443 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
1445 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
1446 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
1447 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
1457 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
1460 switch (rdev->family) {
1488 if (rdev->family == CHIP_RV710)
1494 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
1495 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
1496 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
1498 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
1499 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
1501 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
1502 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
1503 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
1504 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
1505 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
1507 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
1510 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
1511 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
1513 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
1514 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
1516 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
1517 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
1518 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
1519 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
1533 if (rdev->family == CHIP_RV710)
1540 switch (rdev->family) {
1553 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
1599 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1605 dev_warn(rdev->dev, "limiting VRAM\n");
1609 if (rdev->flags & RADEON_IS_AGP) {
1614 dev_warn(rdev->dev, "limiting VRAM\n");
1621 dev_warn(rdev->dev, "limiting VRAM\n");
1628 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1632 radeon_vram_location(rdev, &rdev->mc, 0);
1633 rdev->mc.gtt_base_align = 0;
1634 radeon_gtt_location(rdev, mc);
1638 static int rv770_mc_init(struct radeon_device *rdev)
1644 rdev->mc.vram_is_ddr = true;
1669 rdev->mc.vram_width = numchan * chansize;
1671 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1672 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1674 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1675 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1676 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1677 r700_vram_gtt_location(rdev, &rdev->mc);
1678 radeon_update_bandwidth_info(rdev);
1683 static int rv770_startup(struct radeon_device *rdev)
1689 rv770_pcie_gen2_enable(rdev);
1692 r = r600_vram_scratch_init(rdev);
1696 rv770_mc_program(rdev);
1698 if (rdev->flags & RADEON_IS_AGP) {
1699 rv770_agp_enable(rdev);
1701 r = rv770_pcie_gart_enable(rdev);
1706 rv770_gpu_init(rdev);
1709 r = radeon_wb_init(rdev);
1713 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1715 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1719 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1721 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1725 r = uvd_v2_2_resume(rdev);
1727 r = radeon_fence_driver_start_ring(rdev,
1730 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
1734 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
1737 if (!rdev->irq.installed) {
1738 r = radeon_irq_kms_init(rdev);
1743 r = r600_irq_init(rdev);
1746 radeon_irq_kms_fini(rdev);
1749 r600_irq_set(rdev);
1751 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1752 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1757 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1758 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1763 r = rv770_cp_load_microcode(rdev);
1766 r = r600_cp_resume(rdev);
1770 r = r600_dma_resume(rdev);
1774 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
1776 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
1779 r = uvd_v1_0_init(rdev);
1785 r = radeon_ib_pool_init(rdev);
1787 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1791 r = r600_audio_init(rdev);
1800 int rv770_resume(struct radeon_device *rdev)
1809 atom_asic_init(rdev->mode_info.atom_context);
1812 rv770_init_golden_registers(rdev);
1814 if (rdev->pm.pm_method == PM_METHOD_DPM)
1815 radeon_pm_resume(rdev);
1817 rdev->accel_working = true;
1818 r = rv770_startup(rdev);
1821 rdev->accel_working = false;
1829 int rv770_suspend(struct radeon_device *rdev)
1831 radeon_pm_suspend(rdev);
1832 r600_audio_fini(rdev);
1833 uvd_v1_0_fini(rdev);
1834 radeon_uvd_suspend(rdev);
1835 r700_cp_stop(rdev);
1836 r600_dma_stop(rdev);
1837 r600_irq_suspend(rdev);
1838 radeon_wb_disable(rdev);
1839 rv770_pcie_gart_disable(rdev);
1850 int rv770_init(struct radeon_device *rdev)
1855 if (!radeon_get_bios(rdev)) {
1856 if (ASIC_IS_AVIVO(rdev))
1860 if (!rdev->is_atom_bios) {
1861 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1864 r = radeon_atombios_init(rdev);
1868 if (!radeon_card_posted(rdev)) {
1869 if (!rdev->bios) {
1870 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1874 atom_asic_init(rdev->mode_info.atom_context);
1877 rv770_init_golden_registers(rdev);
1879 r600_scratch_init(rdev);
1881 radeon_surface_init(rdev);
1883 radeon_get_clock_info(rdev->ddev);
1885 r = radeon_fence_driver_init(rdev);
1889 if (rdev->flags & RADEON_IS_AGP) {
1890 r = radeon_agp_init(rdev);
1892 radeon_agp_disable(rdev);
1894 r = rv770_mc_init(rdev);
1898 r = radeon_bo_init(rdev);
1902 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1903 r = r600_init_microcode(rdev);
1911 radeon_pm_init(rdev);
1913 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
1914 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
1916 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
1917 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
1919 r = radeon_uvd_init(rdev);
1921 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
1922 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],
1926 rdev->ih.ring_obj = NULL;
1927 r600_ih_ring_init(rdev, 64 * 1024);
1929 r = r600_pcie_gart_init(rdev);
1933 rdev->accel_working = true;
1934 r = rv770_startup(rdev);
1936 dev_err(rdev->dev, "disabling GPU acceleration\n");
1937 r700_cp_fini(rdev);
1938 r600_dma_fini(rdev);
1939 r600_irq_fini(rdev);
1940 radeon_wb_fini(rdev);
1941 radeon_ib_pool_fini(rdev);
1942 radeon_irq_kms_fini(rdev);
1943 rv770_pcie_gart_fini(rdev);
1944 rdev->accel_working = false;
1950 void rv770_fini(struct radeon_device *rdev)
1952 radeon_pm_fini(rdev);
1953 r700_cp_fini(rdev);
1954 r600_dma_fini(rdev);
1955 r600_irq_fini(rdev);
1956 radeon_wb_fini(rdev);
1957 radeon_ib_pool_fini(rdev);
1958 radeon_irq_kms_fini(rdev);
1959 uvd_v1_0_fini(rdev);
1960 radeon_uvd_fini(rdev);
1961 rv770_pcie_gart_fini(rdev);
1962 r600_vram_scratch_fini(rdev);
1963 radeon_gem_fini(rdev);
1964 radeon_fence_driver_fini(rdev);
1965 radeon_agp_fini(rdev);
1966 radeon_bo_fini(rdev);
1967 radeon_atombios_fini(rdev);
1968 kfree(rdev->bios);
1969 rdev->bios = NULL;
1972 static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1980 if (rdev->flags & RADEON_IS_IGP)
1983 if (!(rdev->flags & RADEON_IS_PCIE))
1987 if (ASIC_IS_X2(rdev))
1990 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
1991 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))