Lines Matching refs:tmp
792 u32 tmp = RREG32(CG_CLKPIN_CNTL);
794 if (tmp & MUX_TCLK_TO_XCLK)
797 if (tmp & XTALIN_DIVIDE)
806 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
810 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
811 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
835 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
836 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
892 u32 tmp;
909 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
913 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
914 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
915 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
917 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
918 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
919 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
920 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
921 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
942 u32 tmp;
955 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
956 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
957 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
958 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
959 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
960 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
961 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
962 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
976 u32 tmp;
986 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
990 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
991 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
992 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
993 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
994 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
995 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
996 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1004 u32 tmp;
1018 tmp = RREG32(HDP_DEBUG1);
1048 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1049 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1050 WREG32(MC_VM_FB_LOCATION, tmp);
1133 u32 tmp, i;
1138 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
1139 tmp &= SCLK_MUX_SEL_MASK;
1140 tmp |= SCLK_MUX_SEL(1) | SCLK_MUX_UPDATE;
1141 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
1149 tmp &= ~SCLK_MUX_UPDATE;
1150 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
1152 tmp = RREG32(MPLL_CNTL_MODE);
1154 tmp &= ~RV730_MPLL_MCLK_SEL;
1156 tmp &= ~MPLL_MCLK_SEL;
1157 WREG32(MPLL_CNTL_MODE, tmp);
1181 u32 db_debug4, tmp;
1300 for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) {
1301 if (!(inactive_pipes & tmp)) {
1304 tmp <<= 1;
1313 tmp = rdev->config.rv770.max_simds -
1315 rdev->config.rv770.active_simds = tmp;
1335 tmp = 0;
1337 tmp |= (1 << i);
1339 if ((disabled_rb_mask & tmp) == tmp) {
1343 tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1344 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
1346 gb_tiling_config |= tmp << 16;
1347 rdev->config.rv770.backend_map = tmp;
1640 u32 tmp;
1645 tmp = RREG32(MC_ARB_RAMCFG);
1646 if (tmp & CHANSIZE_OVERRIDE) {
1648 } else if (tmp & CHANSIZE_MASK) {
1653 tmp = RREG32(MC_SHARED_CHMAP);
1654 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1974 u32 link_width_cntl, lanes, speed_cntl, tmp;
2017 tmp = RREG32(0x541c);
2018 WREG32(0x541c, tmp | 0x8);