Cross Reference: /drivers/gpu/drm/radeon/trinity

Lines Matching refs:ix
587 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
594 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
597 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
604 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix);
607 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value);
614 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
616 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
619 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
626 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
628 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
631 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
639 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
641 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
644 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
646 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
649 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
656 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
658 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);
661 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value);
668 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
670 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);
673 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value);
680 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
682 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
685 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
692 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
694 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
697 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
704 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
706 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix);
709 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix, value);
735 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
737 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
741 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);