Cross Reference: /drivers/gpu/host1x/hw/intr

Lines Matching refs:host
34 	struct host1x *host = syncpt->host;
36 	host1x_sync_writel(host, BIT_MASK(id),
38 	host1x_sync_writel(host, BIT_MASK(id),
41 	queue_work(host->intr_wq, &syncpt->intr.work);
46 	struct host1x *host = dev_id;
50 	for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); i++) {
51 		reg = host1x_sync_readl(host,
55 				host->syncpt + (i * BITS_PER_LONG + id);
63 static void _host1x_intr_disable_all_syncpt_intrs(struct host1x *host)
67 	for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); ++i) {
68 		host1x_sync_writel(host, 0xffffffffu,
70 		host1x_sync_writel(host, 0xffffffffu,
75 static int _host1x_intr_init_host_sync(struct host1x *host, u32 cpm,
80 	host1x_hw_intr_disable_all_syncpt_intrs(host);
82 	for (i = 0; i < host->info->nb_pts; i++)
83 		INIT_WORK(&host->syncpt[i].intr.work, syncpt_thresh_work);
85 	err = devm_request_irq(host->dev, host->intr_syncpt_irq,
87 			       "host1x_syncpt", host);
94 	host1x_sync_writel(host, 0, HOST1X_SYNC_IP_BUSY_TIMEOUT);
100 	host1x_sync_writel(host, 0xff, HOST1X_SYNC_CTXSW_TIMEOUT_CFG);
102 	/* update host clocks per usec */
103 	host1x_sync_writel(host, cpm, HOST1X_SYNC_USEC_CLK);
108 static void _host1x_intr_set_syncpt_threshold(struct host1x *host,
111 	host1x_sync_writel(host, thresh, HOST1X_SYNC_SYNCPT_INT_THRESH(id));
114 static void _host1x_intr_enable_syncpt_intr(struct host1x *host, u32 id)
116 	host1x_sync_writel(host, BIT_MASK(id),
120 static void _host1x_intr_disable_syncpt_intr(struct host1x *host, u32 id)
122 	host1x_sync_writel(host, BIT_MASK(id),
124 	host1x_sync_writel(host, BIT_MASK(id),
128 static int _host1x_free_syncpt_irq(struct host1x *host)
130 	devm_free_irq(host->dev, host->intr_syncpt_irq, host);
131 	flush_workqueue(host->intr_wq);