Lines Matching refs:i2c_dev
237 static void st_i2c_flush_rx_fifo(struct st_i2c_dev *i2c_dev)
246 if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR)
249 count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) &
253 readl_relaxed(i2c_dev->base + SSC_RBUF);
256 static void st_i2c_soft_reset(struct st_i2c_dev *i2c_dev)
262 st_i2c_flush_rx_fifo(i2c_dev);
264 st_i2c_set_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR);
265 st_i2c_clr_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR);
270 * @i2c_dev: Controller's private data
272 static void st_i2c_hw_config(struct st_i2c_dev *i2c_dev)
276 struct st_i2c_timings *t = &i2c_timings[i2c_dev->mode];
278 st_i2c_soft_reset(i2c_dev);
282 writel_relaxed(val, i2c_dev->base + SSC_CLR);
286 writel_relaxed(val, i2c_dev->base + SSC_CTL);
288 rate = clk_get_rate(i2c_dev->clk);
293 writel_relaxed(val, i2c_dev->base + SSC_BRG);
296 writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG);
299 writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C);
303 writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD);
307 writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP);
311 writel_relaxed(val, i2c_dev->base + SSC_START_HOLD);
315 writel_relaxed(val, i2c_dev->base + SSC_DATA_SETUP);
319 writel_relaxed(val, i2c_dev->base + SSC_STOP_SETUP);
323 writel_relaxed(val, i2c_dev->base + SSC_BUS_FREE);
327 writel_relaxed(val, i2c_dev->base + SSC_PRSCALER);
328 writel_relaxed(val, i2c_dev->base + SSC_PRSCALER_DATAOUT);
331 val = i2c_dev->scl_min_width_us * rate / 100000000;
332 writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH);
335 val = i2c_dev->sda_min_width_us * rate / 100000000;
336 writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH_DATAOUT);
339 static int st_i2c_wait_free_bus(struct st_i2c_dev *i2c_dev)
345 sta = readl_relaxed(i2c_dev->base + SSC_STA);
352 dev_err(i2c_dev->dev, "bus not free (status = 0x%08x)\n", sta);
359 * @i2c_dev: Controller's private data
362 static inline void st_i2c_write_tx_fifo(struct st_i2c_dev *i2c_dev, u8 byte)
366 writel_relaxed(tbuf | 1, i2c_dev->base + SSC_TBUF);
371 * @i2c_dev: Controller's private data
376 static void st_i2c_wr_fill_tx_fifo(struct st_i2c_dev *i2c_dev)
378 struct st_i2c_client *c = &i2c_dev->client;
382 sta = readl_relaxed(i2c_dev->base + SSC_STA);
386 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT);
395 st_i2c_write_tx_fifo(i2c_dev, *c->buf);
400 * @i2c_dev: Controller's private data
405 static void st_i2c_rd_fill_tx_fifo(struct st_i2c_dev *i2c_dev, int max)
407 struct st_i2c_client *c = &i2c_dev->client;
411 sta = readl_relaxed(i2c_dev->base + SSC_STA);
415 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT);
424 st_i2c_write_tx_fifo(i2c_dev, 0xff);
427 static void st_i2c_read_rx_fifo(struct st_i2c_dev *i2c_dev)
429 struct st_i2c_client *c = &i2c_dev->client;
433 sta = readl_relaxed(i2c_dev->base + SSC_STA);
437 i = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT);
442 rbuf = readl_relaxed(i2c_dev->base + SSC_RBUF) >> 1;
447 dev_err(i2c_dev->dev, "Unexpected %d bytes in rx fifo\n", i);
448 st_i2c_flush_rx_fifo(i2c_dev);
454 * @i2c_dev: Controller's private data
456 static void st_i2c_terminate_xfer(struct st_i2c_dev *i2c_dev)
458 struct st_i2c_client *c = &i2c_dev->client;
460 st_i2c_clr_bits(i2c_dev->base + SSC_IEN, SSC_IEN_TEEN);
461 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG);
464 st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_STOPEN);
465 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
467 st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_REPSTRTEN);
468 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_REPSTRTG);
474 * @i2c_dev: Controller's private data
476 static void st_i2c_handle_write(struct st_i2c_dev *i2c_dev)
478 struct st_i2c_client *c = &i2c_dev->client;
480 st_i2c_flush_rx_fifo(i2c_dev);
484 st_i2c_terminate_xfer(i2c_dev);
486 st_i2c_wr_fill_tx_fifo(i2c_dev);
491 * @i2c_dev: Controller's private data
493 static void st_i2c_handle_read(struct st_i2c_dev *i2c_dev)
495 struct st_i2c_client *c = &i2c_dev->client;
500 readl_relaxed(i2c_dev->base + SSC_RBUF);
501 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_TXENB);
503 st_i2c_read_rx_fifo(i2c_dev);
508 st_i2c_terminate_xfer(i2c_dev);
511 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_ACKG);
515 writel_relaxed(ien, i2c_dev->base + SSC_IEN);
517 st_i2c_rd_fill_tx_fifo(i2c_dev, c->count);
519 st_i2c_rd_fill_tx_fifo(i2c_dev, c->count - 1);
530 struct st_i2c_dev *i2c_dev = data;
531 struct st_i2c_client *c = &i2c_dev->client;
535 ien = readl_relaxed(i2c_dev->base + SSC_IEN);
536 sta = readl_relaxed(i2c_dev->base + SSC_STA);
541 dev_dbg(i2c_dev->dev, "spurious it (sta=0x%04x, ien=0x%04x)\n",
549 st_i2c_handle_read(i2c_dev);
551 st_i2c_handle_write(i2c_dev);
556 writel_relaxed(0, i2c_dev->base + SSC_IEN);
557 complete(&i2c_dev->complete);
561 writel_relaxed(SSC_CLR_NACK, i2c_dev->base + SSC_CLR);
565 st_i2c_handle_read(i2c_dev);
570 writel_relaxed(it, i2c_dev->base + SSC_IEN);
572 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
577 writel_relaxed(SSC_CLR_SSCARBL, i2c_dev->base + SSC_CLR);
580 writel_relaxed(it, i2c_dev->base + SSC_IEN);
582 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
587 dev_err(i2c_dev->dev,
596 readl(i2c_dev->base + SSC_IEN);
603 * @i2c_dev: Controller's private data
608 static int st_i2c_xfer_msg(struct st_i2c_dev *i2c_dev, struct i2c_msg *msg,
611 struct st_i2c_client *c = &i2c_dev->client;
624 reinit_completion(&i2c_dev->complete);
627 st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl);
632 st_i2c_set_bits(i2c_dev->base + SSC_I2C, i2c);
635 st_i2c_write_tx_fifo(i2c_dev, c->addr);
639 st_i2c_wr_fill_tx_fifo(i2c_dev);
642 writel_relaxed(it, i2c_dev->base + SSC_IEN);
645 ret = st_i2c_wait_free_bus(i2c_dev);
649 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG);
652 timeout = wait_for_completion_timeout(&i2c_dev->complete,
653 i2c_dev->adap.timeout);
657 dev_err(i2c_dev->dev, "Write to slave 0x%x timed out\n",
663 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, i2c);
666 i2c_dev->base + SSC_CLR);
680 struct st_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
683 i2c_dev->busy = true;
685 ret = clk_prepare_enable(i2c_dev->clk);
687 dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n");
691 pinctrl_pm_select_default_state(i2c_dev->dev);
693 st_i2c_hw_config(i2c_dev);
696 ret = st_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0, i == num - 1);
698 pinctrl_pm_select_idle_state(i2c_dev->dev);
700 clk_disable_unprepare(i2c_dev->clk);
702 i2c_dev->busy = false;
712 struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
714 if (i2c_dev->busy)
748 struct st_i2c_dev *i2c_dev)
753 &i2c_dev->scl_min_width_us);
755 dev_err(i2c_dev->dev, "st,i2c-min-scl-pulse-width-us invalid\n");
760 &i2c_dev->sda_min_width_us);
762 dev_err(i2c_dev->dev, "st,i2c-min-sda-pulse-width-us invalid\n");
772 struct st_i2c_dev *i2c_dev;
778 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
779 if (!i2c_dev)
783 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
784 if (IS_ERR(i2c_dev->base))
785 return PTR_ERR(i2c_dev->base);
787 i2c_dev->irq = irq_of_parse_and_map(np, 0);
788 if (!i2c_dev->irq) {
793 i2c_dev->clk = of_clk_get_by_name(np, "ssc");
794 if (IS_ERR(i2c_dev->clk)) {
796 return PTR_ERR(i2c_dev->clk);
799 i2c_dev->mode = I2C_MODE_STANDARD;
802 i2c_dev->mode = I2C_MODE_FAST;
804 i2c_dev->dev = &pdev->dev;
806 ret = devm_request_threaded_irq(&pdev->dev, i2c_dev->irq,
808 IRQF_ONESHOT, pdev->name, i2c_dev);
810 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
814 pinctrl_pm_select_default_state(i2c_dev->dev);
816 pinctrl_pm_select_idle_state(i2c_dev->dev);
818 ret = st_i2c_of_get_deglitch(np, i2c_dev);
822 adap = &i2c_dev->adap;
823 i2c_set_adapdata(adap, i2c_dev);
832 init_completion(&i2c_dev->complete);
840 platform_set_drvdata(pdev, i2c_dev);
842 dev_info(i2c_dev->dev, "%s initialized\n", adap->name);
849 struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
851 i2c_del_adapter(&i2c_dev->adap);