Lines Matching refs:dd
74 * @dd: the infinipath device
87 static int create_port0_egr(struct ipath_devdata *dd)
93 egrcnt = dd->ipath_p0_rcvegrcnt;
95 skbinfo = vmalloc(sizeof(*dd->ipath_port0_skbinfo) * egrcnt);
97 ipath_dev_err(dd, "allocation error for eager TID "
111 skbinfo[e].skb = ipath_alloc_skb(dd, GFP_KERNEL);
113 ipath_dev_err(dd, "SKB allocation error for "
126 dd->ipath_port0_skbinfo = skbinfo;
129 dd->ipath_port0_skbinfo[e].phys =
130 ipath_map_single(dd->pcidev,
131 dd->ipath_port0_skbinfo[e].skb->data,
132 dd->ipath_ibmaxlen, PCI_DMA_FROMDEVICE);
133 dd->ipath_f_put_tid(dd, e + (u64 __iomem *)
134 ((char __iomem *) dd->ipath_kregbase +
135 dd->ipath_rcvegrbase),
137 dd->ipath_port0_skbinfo[e].phys);
146 static int bringup_link(struct ipath_devdata *dd)
152 dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
153 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
154 dd->ipath_control);
160 val = (dd->ipath_ibmaxlen >> 2) + 1;
161 ibc = val << dd->ibcc_mpl_shift;
178 dd->ipath_ibcctrl = ibc;
188 dd->ipath_flags |= IPATH_IB_LINK_DISABLED;
191 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc);
194 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
196 ret = dd->ipath_f_bringup_serdes(dd);
199 dev_info(&dd->pcidev->dev, "Could not initialize SerDes, "
203 dd->ipath_control |= INFINIPATH_C_LINKENABLE;
204 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
205 dd->ipath_control);
211 static struct ipath_portdata *create_portdata0(struct ipath_devdata *dd)
217 pd->port_dd = dd;
226 static int init_chip_first(struct ipath_devdata *dd)
232 spin_lock_init(&dd->ipath_kernel_tid_lock);
233 spin_lock_init(&dd->ipath_user_tid_lock);
234 spin_lock_init(&dd->ipath_sendctrl_lock);
235 spin_lock_init(&dd->ipath_uctxt_lock);
236 spin_lock_init(&dd->ipath_sdma_lock);
237 spin_lock_init(&dd->ipath_gpio_lock);
238 spin_lock_init(&dd->ipath_eep_st_lock);
239 spin_lock_init(&dd->ipath_sdepb_lock);
240 mutex_init(&dd->ipath_eep_lock);
248 dd->ipath_f_config_ports(dd, ipath_cfgports);
250 dd->ipath_cfgports = dd->ipath_portcnt;
251 else if (ipath_cfgports <= dd->ipath_portcnt) {
252 dd->ipath_cfgports = ipath_cfgports;
254 dd->ipath_cfgports, ipath_read_kreg32(dd,
255 dd->ipath_kregs->kr_portcnt));
257 dd->ipath_cfgports = dd->ipath_portcnt;
260 ipath_read_kreg32(dd,
261 dd->ipath_kregs->kr_portcnt));
267 dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_portcnt,
270 if (!dd->ipath_pd) {
271 ipath_dev_err(dd, "Unable to allocate portdata array, "
277 pd = create_portdata0(dd);
279 ipath_dev_err(dd, "Unable to allocate portdata for port "
284 dd->ipath_pd[0] = pd;
286 dd->ipath_rcvtidcnt =
287 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
288 dd->ipath_rcvtidbase =
289 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
290 dd->ipath_rcvegrcnt =
291 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
292 dd->ipath_rcvegrbase =
293 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
294 dd->ipath_palign =
295 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
296 dd->ipath_piobufbase =
297 ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase);
298 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize);
299 dd->ipath_piosize2k = val & ~0U;
300 dd->ipath_piosize4k = val >> 32;
301 if (dd->ipath_piosize4k == 0 && ipath_mtu4096)
303 dd->ipath_ibmtu = ipath_mtu4096 ? 4096 : 2048;
304 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt);
305 dd->ipath_piobcnt2k = val & ~0U;
306 dd->ipath_piobcnt4k = val >> 32;
307 dd->ipath_pio2kbase =
308 (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) +
309 (dd->ipath_piobufbase & 0xffffffff));
310 if (dd->ipath_piobcnt4k) {
311 dd->ipath_pio4kbase = (u32 __iomem *)
312 (((char __iomem *) dd->ipath_kregbase) +
313 (dd->ipath_piobufbase >> 32));
319 dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k,
320 dd->ipath_palign);
323 dd->ipath_piobcnt2k, dd->ipath_piosize2k,
324 dd->ipath_pio2kbase, dd->ipath_piobcnt4k,
325 dd->ipath_piosize4k, dd->ipath_pio4kbase,
326 dd->ipath_4kalign);
329 dd->ipath_piobcnt2k, dd->ipath_pio2kbase);
337 * @dd: the infinipath device
343 static int init_chip_reset(struct ipath_devdata *dd)
353 dd->ipath_rcvctrl &= ~(1ULL << dd->ipath_r_tailupd_shift);
354 for (i = 0; i < dd->ipath_portcnt; i++) {
355 clear_bit(dd->ipath_r_portenable_shift + i,
356 &dd->ipath_rcvctrl);
357 clear_bit(dd->ipath_r_intravail_shift + i,
358 &dd->ipath_rcvctrl);
360 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
361 dd->ipath_rcvctrl);
363 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
364 dd->ipath_sendctrl = 0U; /* no sdma, etc */
365 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
366 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
367 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
369 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
371 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
372 if (rtmp != dd->ipath_rcvtidcnt)
373 dev_info(&dd->pcidev->dev, "tidcnt was %u before "
375 dd->ipath_rcvtidcnt, rtmp);
376 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
377 if (rtmp != dd->ipath_rcvtidbase)
378 dev_info(&dd->pcidev->dev, "tidbase was %u before "
380 dd->ipath_rcvtidbase, rtmp);
381 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
382 if (rtmp != dd->ipath_rcvegrcnt)
383 dev_info(&dd->pcidev->dev, "egrcnt was %u before "
385 dd->ipath_rcvegrcnt, rtmp);
386 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
387 if (rtmp != dd->ipath_rcvegrbase)
388 dev_info(&dd->pcidev->dev, "egrbase was %u before "
390 dd->ipath_rcvegrbase, rtmp);
395 static int init_pioavailregs(struct ipath_devdata *dd)
399 dd->ipath_pioavailregs_dma = dma_alloc_coherent(
400 &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys,
402 if (!dd->ipath_pioavailregs_dma) {
403 ipath_dev_err(dd, "failed to allocate PIOavail reg area "
413 dd->ipath_statusp = (u64 *)
414 ((char *)dd->ipath_pioavailregs_dma +
416 dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
418 *dd->ipath_statusp = dd->_ipath_status;
423 dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1];
425 dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]);
435 * @dd: the infinipath device
442 static void init_shadow_tids(struct ipath_devdata *dd)
447 pages = vzalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
450 ipath_dev_err(dd, "failed to allocate shadow page * "
452 dd->ipath_pageshadow = NULL;
456 addrs = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
459 ipath_dev_err(dd, "failed to allocate shadow dma handle "
462 dd->ipath_pageshadow = NULL;
466 dd->ipath_pageshadow = pages;
467 dd->ipath_physshadow = addrs;
470 static void enable_chip(struct ipath_devdata *dd, int reinit)
480 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
481 dd->ipath_rcvctrl);
483 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
485 dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE |
492 if (dd->ipath_pioupd_thresh)
493 dd->ipath_sendctrl |= dd->ipath_pioupd_thresh
495 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
496 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
497 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
504 dd->ipath_rcvctrl |= (rcvmask << dd->ipath_r_portenable_shift) |
505 (rcvmask << dd->ipath_r_intravail_shift);
506 if (!(dd->ipath_flags & IPATH_NODMA_RTAIL))
507 dd->ipath_rcvctrl |= (1ULL << dd->ipath_r_tailupd_shift);
509 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
510 dd->ipath_rcvctrl);
516 dd->ipath_flags |= IPATH_INITTED;
522 val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0);
523 ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0);
526 ipath_write_ureg(dd, ur_rcvhdrhead,
527 dd->ipath_rhdrhead_intr_off |
528 dd->ipath_pd[0]->port_head, 0);
536 for (i = 0; i < dd->ipath_pioavregs; i++) {
542 if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS))
543 pioavail = dd->ipath_pioavailregs_dma[i ^ 1];
545 pioavail = dd->ipath_pioavailregs_dma[i];
551 dd->ipath_pioavailshadow[i] = le64_to_cpu(pioavail);
554 dd->ipath_flags |= IPATH_PRESENT;
557 static int init_housekeeping(struct ipath_devdata *dd, int reinit)
567 dd->ipath_rcvhdrsize = 0;
577 dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT;
578 dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED |
582 dd->ipath_revision =
583 ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
590 dd->ipath_sregbase =
591 ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase);
592 dd->ipath_cregbase =
593 ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase);
594 dd->ipath_uregbase =
595 ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase);
597 "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase,
598 dd->ipath_uregbase, dd->ipath_cregbase);
599 if ((dd->ipath_revision & 0xffffffff) == 0xffffffff
600 || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff
601 || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff
602 || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) {
603 ipath_dev_err(dd, "Register read failures from chip, "
605 dd->ipath_flags &= ~IPATH_PRESENT;
612 ipath_write_kreg (dd, dd->ipath_kregs->kr_hwdiagctrl, 0);
615 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
619 (unsigned long long) dd->ipath_revision,
620 dd->ipath_pcirev);
622 if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) &
624 ipath_dev_err(dd, "Driver only handles version %d, "
627 (int)(dd->ipath_revision >>
630 (unsigned long long) dd->ipath_revision);
634 dd->ipath_majrev = (u8) ((dd->ipath_revision >>
637 dd->ipath_minrev = (u8) ((dd->ipath_revision >>
640 dd->ipath_boardrev = (u8) ((dd->ipath_revision >>
644 ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn);
646 snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion),
650 (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) &
652 dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev,
653 (unsigned)(dd->ipath_revision >>
657 ipath_dbg("%s", dd->ipath_boardversion);
663 ret = init_chip_reset(dd);
665 ret = init_chip_first(dd);
673 struct ipath_devdata *dd = (struct ipath_devdata *) opaque;
675 if (!dd)
682 if (dd->ipath_int_counter == 0) {
683 if (!dd->ipath_f_intr_fallback(dd))
684 dev_err(&dd->pcidev->dev, "No interrupts detected, "
687 mod_timer(&dd->ipath_intrchk_timer, jiffies + HZ/2);
690 dd->ipath_int_counter);
695 * @dd: the infinipath device
708 int ipath_init_chip(struct ipath_devdata *dd, int reinit)
717 ret = init_housekeeping(dd, reinit);
727 dd->ipath_rcvhdrcnt = max(dd->ipath_p0_rcvegrcnt, dd->ipath_rcvegrcnt);
728 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt,
729 dd->ipath_rcvhdrcnt);
737 piobufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
742 dd->ipath_pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2)
744 uports = dd->ipath_cfgports ? dd->ipath_cfgports - 1 : 0;
746 defkbufs = 32 + dd->ipath_pioreserved;
748 defkbufs = 16 + dd->ipath_pioreserved;
756 dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs of "
769 dd->ipath_lastport_piobuf = piobufs - kpiobufs;
770 dd->ipath_pbufsport =
771 uports ? dd->ipath_lastport_piobuf / uports : 0;
773 dd->ipath_ports_extrabuf = dd->ipath_lastport_piobuf -
774 (dd->ipath_pbufsport * uports);
775 if (dd->ipath_ports_extrabuf)
777 "ports <= %u\n", dd->ipath_pbufsport,
778 dd->ipath_ports_extrabuf);
779 dd->ipath_lastpioindex = 0;
780 dd->ipath_lastpioindexl = dd->ipath_piobcnt2k;
784 piobufs, dd->ipath_pbufsport, uports);
785 ret = dd->ipath_f_early_init(dd);
787 ipath_dev_err(dd, "Early initialization failure\n");
795 dd->ipath_hdrqlast =
796 dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1);
797 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize,
798 dd->ipath_rcvhdrentsize);
799 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
800 dd->ipath_rcvhdrsize);
803 ret = init_pioavailregs(dd);
804 init_shadow_tids(dd);
809 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr,
810 dd->ipath_pioavailregs_phys);
816 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr);
817 if (val != dd->ipath_pioavailregs_phys) {
818 ipath_dev_err(dd, "Catastrophic software error, "
821 (unsigned long) dd->ipath_pioavailregs_phys,
827 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP);
833 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL);
834 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
836 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
842 if (bringup_link(dd)) {
843 dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n");
853 dd->ipath_f_init_hwerrors(dd);
854 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
856 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
857 dd->ipath_hwerrmask);
860 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
862 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
863 ~dd->ipath_maskederrs);
864 dd->ipath_maskederrs = 0; /* don't re-enable ignored in timer */
865 dd->ipath_errormask =
866 ipath_read_kreg64(dd, dd->ipath_kregs->kr_errormask);
868 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
870 dd->ipath_f_tidtemplate(dd);
878 pd = dd->ipath_pd[0];
887 npd = create_portdata0(dd);
889 ipath_free_pddata(dd, pd);
890 dd->ipath_pd[0] = npd;
893 ipath_dev_err(dd, "Unable to allocate portdata"
899 ret = ipath_create_rcvhdrq(dd, pd);
901 ret = create_port0_egr(dd);
903 ipath_dev_err(dd, "failed to allocate kernel port's "
908 enable_chip(dd, reinit);
911 ipath_chg_pioavailkernel(dd, 0, piobufs, 1);
921 ipath_cancel_sends(dd, 1);
928 dd->ipath_dummy_hdrq = dma_alloc_coherent(
929 &dd->pcidev->dev, dd->ipath_pd[0]->port_rcvhdrq_size,
930 &dd->ipath_dummy_hdrq_phys,
932 if (!dd->ipath_dummy_hdrq) {
933 dev_info(&dd->pcidev->dev,
935 dd->ipath_pd[0]->port_rcvhdrq_size);
937 dd->ipath_dummy_hdrq_phys = 0UL;
945 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
947 if (!dd->ipath_stats_timer_active) {
953 init_timer(&dd->ipath_stats_timer);
954 dd->ipath_stats_timer.function = ipath_get_faststats;
955 dd->ipath_stats_timer.data = (unsigned long) dd;
957 dd->ipath_stats_timer.expires = jiffies + 5 * HZ;
959 add_timer(&dd->ipath_stats_timer);
960 dd->ipath_stats_timer_active = 1;
964 if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
965 ret = setup_sdma(dd);
968 init_timer(&dd->ipath_hol_timer);
969 dd->ipath_hol_timer.function = ipath_hol_event;
970 dd->ipath_hol_timer.data = (unsigned long)dd;
971 dd->ipath_hol_state = IPATH_HOL_UP;
975 *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT;
976 if (!dd->ipath_f_intrsetup(dd)) {
978 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
981 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear,
984 *dd->ipath_statusp |= IPATH_STATUS_INITTED;
991 init_timer(&dd->ipath_intrchk_timer);
992 dd->ipath_intrchk_timer.function =
994 dd->ipath_intrchk_timer.data =
995 (unsigned long) dd;
997 dd->ipath_intrchk_timer.expires = jiffies + HZ/2;
998 add_timer(&dd->ipath_intrchk_timer);
1000 ipath_dev_err(dd, "No interrupts enabled, couldn't "
1003 if (dd->ipath_cfgports > ipath_stats.sps_nports)
1012 ipath_stats.sps_nports = dd->ipath_cfgports;
1023 struct ipath_devdata *dd;
1040 list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
1041 if (dd->ipath_kregbase)
1043 if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
1044 (dd->ipath_cfgports *
1048 dd,
1051 val, dd->ipath_cfgports - 1,
1056 dd->ipath_lastport_piobuf =
1057 dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val;