Cross Reference: /drivers/infiniband/hw/mlx5/mr.c

Lines Matching refs:cache
59 	struct mlx5_mr_cache *cache = &dev->cache;
61 	if (order < cache->ent[0].order)
64 		return order - cache->ent[0].order;
71 	struct mlx5_mr_cache *cache = &dev->cache;
73 	struct mlx5_cache_ent *ent = &cache->ent[c];
105 	cache->last_add = jiffies;
123 	struct mlx5_mr_cache *cache = &dev->cache;
124 	struct mlx5_cache_ent *ent = &cache->ent[c];
174 	struct mlx5_mr_cache *cache = &dev->cache;
175 	struct mlx5_cache_ent *ent = &cache->ent[c];
327 static int someone_adding(struct mlx5_mr_cache *cache)
332 		if (cache->ent[i].cur < cache->ent[i].limit)
342 	struct mlx5_mr_cache *cache = &dev->cache;
346 	if (cache->stopped)
349 	ent = &dev->cache.ent[i];
356 				queue_delayed_work(cache->wq, &ent->dwork,
361 				queue_delayed_work(cache->wq, &ent->dwork,
364 				queue_work(cache->wq, &ent->work);
368 		if (!someone_adding(cache) &&
369 		    time_after(jiffies, cache->last_add + 300 * HZ)) {
372 				queue_work(cache->wq, &ent->work);
374 			queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ);
397 	struct mlx5_mr_cache *cache = &dev->cache;
405 		mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c);
410 		ent = &cache->ent[i];
412 		mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i);
422 				queue_work(cache->wq, &ent->work);
427 		queue_work(cache->wq, &ent->work);
434 		cache->ent[c].miss++;
441 	struct mlx5_mr_cache *cache = &dev->cache;
448 		mlx5_ib_warn(dev, "order %d, cache index %d\n", mr->order, c);
451 	ent = &cache->ent[c];
460 		queue_work(cache->wq, &ent->work);
465 	struct mlx5_mr_cache *cache = &dev->cache;
466 	struct mlx5_cache_ent *ent = &cache->ent[c];
492 	struct mlx5_mr_cache *cache = &dev->cache;
499 	cache->root = debugfs_create_dir("mr_cache", dev->mdev->priv.dbg_root);
500 	if (!cache->root)
504 		ent = &cache->ent[i];
506 		ent->dir = debugfs_create_dir(ent->name,  cache->root);
539 	debugfs_remove_recursive(dev->cache.root);
551 	struct mlx5_mr_cache *cache = &dev->cache;
557 	cache->wq = create_singlethread_workqueue("mkey_cache");
558 	if (!cache->wq) {
565 		INIT_LIST_HEAD(&cache->ent[i].head);
566 		spin_lock_init(&cache->ent[i].lock);
568 		ent = &cache->ent[i];
582 		queue_work(cache->wq, &ent->work);
587 		mlx5_ib_warn(dev, "cache debugfs failure\n");
596 	dev->cache.stopped = 1;
597 	flush_workqueue(dev->cache.wq);
604 	destroy_workqueue(dev->cache.wq);
907 			mlx5_ib_dbg(dev, "cache empty for order %d", order);