Lines Matching refs:SYM_LSB
181 (((value) >> SYM_LSB(regname, fldname)) & \
186 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))
197 #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB)
369 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
371 SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))
465 #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
466 #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)
668 SYM_LSB(IntStatus, SendBufAvail), 0, 0},
670 SYM_LSB(IntStatus, SDmaInt_0), 1, 1 },
672 SYM_LSB(IntStatus, SDmaInt_1), 2, 1 },
674 SYM_LSB(IntStatus, SDmaIdleInt_0), 1, 1},
676 SYM_LSB(IntStatus, SDmaIdleInt_1), 2, 1},
678 SYM_LSB(IntStatus, SDmaProgressInt_0), 1, 1 },
680 SYM_LSB(IntStatus, SDmaProgressInt_1), 2, 1 },
682 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1, 0 },
684 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 , 0},
695 { 0, SYM_LSB(DCACtrlB, RcvHdrq0DCAOPH),
697 { 0, SYM_LSB(DCACtrlB, RcvHdrq1DCAOPH),
699 { 0, SYM_LSB(DCACtrlB, RcvHdrq2DCAOPH),
701 { 0, SYM_LSB(DCACtrlB, RcvHdrq3DCAOPH),
703 { 1, SYM_LSB(DCACtrlC, RcvHdrq4DCAOPH),
705 { 1, SYM_LSB(DCACtrlC, RcvHdrq5DCAOPH),
707 { 1, SYM_LSB(DCACtrlC, RcvHdrq6DCAOPH),
709 { 1, SYM_LSB(DCACtrlC, RcvHdrq7DCAOPH),
711 { 2, SYM_LSB(DCACtrlD, RcvHdrq8DCAOPH),
713 { 2, SYM_LSB(DCACtrlD, RcvHdrq9DCAOPH),
715 { 2, SYM_LSB(DCACtrlD, RcvHdrq10DCAOPH),
717 { 2, SYM_LSB(DCACtrlD, RcvHdrq11DCAOPH),
719 { 3, SYM_LSB(DCACtrlE, RcvHdrq12DCAOPH),
721 { 3, SYM_LSB(DCACtrlE, RcvHdrq13DCAOPH),
723 { 3, SYM_LSB(DCACtrlE, RcvHdrq14DCAOPH),
725 { 3, SYM_LSB(DCACtrlE, RcvHdrq15DCAOPH),
727 { 4, SYM_LSB(DCACtrlF, RcvHdrq16DCAOPH),
729 { 4, SYM_LSB(DCACtrlF, RcvHdrq17DCAOPH),
940 #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
943 #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
1149 #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)
1164 #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)
1166 #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
1167 #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)
1170 #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1171 #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1174 #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1178 SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
1179 #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)
1292 SYM_LSB(IntMask, fldname##Mask##_0), \
1293 SYM_LSB(IntMask, fldname##Mask##_1)), \
1297 SYM_LSB(IntMask, fldname##Mask##_1), \
1298 SYM_LSB(IntMask, fldname##Mask##_0)), \
1305 SYM_LSB(IntMask, fldname##0IntMask), \
1306 SYM_LSB(IntMask, fldname##17IntMask)), \
2366 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane));
2412 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark);
2418 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod);
2420 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
2422 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold);
2428 SYM_LSB(IBCCtrlA_0, MaxPktLen);
2481 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH);
2742 SYM_LSB(DCACtrlF, SendDma1DCAOPH) :
2743 SYM_LSB(DCACtrlF, SendDma0DCAOPH));
2766 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq0DCAXfrCnt)) |
2767 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq1DCAXfrCnt)) |
2768 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq2DCAXfrCnt)) |
2769 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq3DCAXfrCnt));
2771 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq4DCAXfrCnt)) |
2772 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq5DCAXfrCnt)) |
2773 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq6DCAXfrCnt)) |
2774 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq7DCAXfrCnt));
2776 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq8DCAXfrCnt)) |
2777 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq9DCAXfrCnt)) |
2778 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq10DCAXfrCnt)) |
2779 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq11DCAXfrCnt));
2781 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq12DCAXfrCnt)) |
2782 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq13DCAXfrCnt)) |
2783 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq14DCAXfrCnt)) |
2784 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq15DCAXfrCnt));
2786 (1ULL << SYM_LSB(DCACtrlF, RcvHdrq16DCAXfrCnt)) |
2787 (1ULL << SYM_LSB(DCACtrlF, RcvHdrq17DCAXfrCnt));
3007 pins >>= SYM_LSB(EXTStatus, GPIOIn);
3537 SYM_LSB(IntRedirect0, vec1);
3974 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg);
3976 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg);
3980 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode);
4023 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
4028 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
4140 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS);
4165 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE);
4169 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
4174 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
4185 SYM_LSB(IBCCtrlA_0, OverrunThreshold);
4199 SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
4236 SYM_LSB(IBCCtrlA_0, MaxPktLen);
4399 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) &
4401 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) &
4415 SYM_LSB(LowPriority0_0, VirtualLane)) |
4417 SYM_LSB(LowPriority0_0, Weight));
4549 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4563 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4565 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull);
4567 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull));
4569 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail));
4571 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail));
4721 SYM_LSB(SendCtrl, DisarmSendBuf));
5751 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5752 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
6073 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert));
6295 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP);
6740 << SYM_LSB(SendCtrl, AvailUpdThld)) |
7163 SYM_LSB(SendCtrl, AvailUpdThld);
7183 << SYM_LSB(SendCtrl, AvailUpdThld);
7776 #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address)
7777 #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data)
8247 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8250 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8253 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8256 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8296 #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en)