Lines Matching refs:dd
131 * Do remaining PCIe setup, once dd is allocated, and save away
135 int qib_pcie_ddinit(struct qib_devdata *dd, struct pci_dev *pdev,
141 dd->pcidev = pdev;
142 pci_set_drvdata(pdev, dd);
149 dd->kregbase = __ioremap(addr, len, _PAGE_NO_CACHE | _PAGE_WRITETHRU);
151 dd->kregbase = ioremap_nocache(addr, len);
154 if (!dd->kregbase)
157 dd->kregend = (u64 __iomem *)((void __iomem *) dd->kregbase + len);
158 dd->physaddr = addr; /* used for io_remap, etc. */
164 dd->pcibar0 = addr;
165 dd->pcibar1 = addr >> 32;
166 dd->deviceid = ent->device; /* save for later use */
167 dd->vendorid = ent->vendor;
174 * to releasing the dd memory.
177 void qib_pcie_ddcleanup(struct qib_devdata *dd)
179 u64 __iomem *base = (void __iomem *) dd->kregbase;
181 dd->kregbase = NULL;
183 if (dd->piobase)
184 iounmap(dd->piobase);
185 if (dd->userbase)
186 iounmap(dd->userbase);
187 if (dd->piovl15base)
188 iounmap(dd->piovl15base);
190 pci_disable_device(dd->pcidev);
191 pci_release_regions(dd->pcidev);
193 pci_set_drvdata(dd->pcidev, NULL);
196 static void qib_msix_setup(struct qib_devdata *dd, int pos, u32 *msixcnt,
204 ret = pci_msix_vec_count(dd->pcidev);
220 ret = pci_enable_msix_range(dd->pcidev, msix_entry, 1, nvec);
237 qib_dev_err(dd, "pci_enable_msix_range %d vectors failed: %d, "
240 qib_enable_intx(dd->pcidev);
248 static int qib_msi_setup(struct qib_devdata *dd, int pos)
250 struct pci_dev *pdev = dd->pcidev;
256 qib_dev_err(dd,
262 &dd->msi_lo);
264 &dd->msi_hi);
269 &dd->msi_data);
273 int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent,
279 if (!pci_is_pcie(dd->pcidev)) {
280 qib_dev_err(dd, "Can't find PCI Express capability!\n");
282 dd->lbus_width = 1;
283 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
287 pos = dd->pcidev->msix_cap;
289 qib_msix_setup(dd, pos, nent, entry);
292 pos = dd->pcidev->msi_cap;
294 ret = qib_msi_setup(dd, pos);
296 qib_dev_err(dd, "No PCI MSI or MSIx capability!\n");
299 qib_enable_intx(dd->pcidev);
301 pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);
309 dd->lbus_width = linkstat;
313 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
316 dd->lbus_speed = 5000; /* Gen1, 5GHz */
319 dd->lbus_speed = 2500;
328 qib_dev_err(dd,
332 qib_tune_pcie_caps(dd);
334 qib_tune_pcie_coalesce(dd);
338 snprintf(dd->lbus_info, sizeof(dd->lbus_info),
339 "PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width);
351 int qib_reinit_intr(struct qib_devdata *dd)
358 if (!dd->msi_lo)
361 pos = dd->pcidev->msi_cap;
363 qib_dev_err(dd,
369 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
370 dd->msi_lo);
371 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
372 dd->msi_hi);
373 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
376 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
380 pci_write_config_word(dd->pcidev, pos +
382 dd->msi_data);
385 if (!ret && (dd->flags & QIB_HAS_INTX)) {
386 qib_enable_intx(dd->pcidev);
391 pci_set_master(dd->pcidev);
401 void qib_nomsi(struct qib_devdata *dd)
403 dd->msi_lo = 0;
404 pci_disable_msi(dd->pcidev);
410 void qib_nomsix(struct qib_devdata *dd)
412 pci_disable_msix(dd->pcidev);
452 void qib_pcie_getcmd(struct qib_devdata *dd, u16 *cmd, u8 *iline, u8 *cline)
454 pci_read_config_word(dd->pcidev, PCI_COMMAND, cmd);
455 pci_read_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);
456 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
459 void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline)
462 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
463 dd->pcibar0);
465 qib_dev_err(dd, "rewrite of BAR0 failed: %d\n", r);
466 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
467 dd->pcibar1);
469 qib_dev_err(dd, "rewrite of BAR1 failed: %d\n", r);
471 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmd);
472 pci_write_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);
473 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
474 r = pci_enable_device(dd->pcidev);
476 qib_dev_err(dd,
491 static void qib_tune_pcie_coalesce(struct qib_devdata *dd)
502 parent = dd->pcidev->bus->self;
504 qib_devinfo(dd->pcidev, "Parent not root\n");
559 static void qib_tune_pcie_caps(struct qib_devdata *dd)
566 parent = dd->pcidev->bus->self;
568 qib_devinfo(dd->pcidev, "Parent not root\n");
572 if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev))
578 ep_mpss = dd->pcidev->pcie_mpss;
579 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8;
596 pcie_set_mps(dd->pcidev, 128 << ep_mps);
610 ep_mrrs = pcie_get_readrq(dd->pcidev);
618 pcie_set_readrq(dd->pcidev, ep_mrrs);
630 struct qib_devdata *dd = pci_get_drvdata(pdev);
646 if (dd) {
648 dd->flags &= ~QIB_PRESENT;
649 qib_disable_after_error(dd);
667 struct qib_devdata *dd = pci_get_drvdata(pdev);
670 if (dd && dd->pport) {
671 words = dd->f_portcntr(dd->pport, QIBPORTCNTR_WORDRCV);
698 struct qib_devdata *dd = pci_get_drvdata(pdev);
706 qib_init(dd, 1); /* same as re-init after reset */