Cross Reference: /drivers/irqchip/irq-atmel-aic5.c

Lines Matching refs:reg_base
78 	irqnr = irq_reg_readl(gc->reg_base + AT91_AIC5_IVR);
79 	irqstat = irq_reg_readl(gc->reg_base + AT91_AIC5_ISR);
82 		irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR);
95 	irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
96 	irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR);
109 	irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
110 	irq_reg_writel(1, gc->reg_base + AT91_AIC5_IECR);
123 	irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
124 	irq_reg_writel(1, gc->reg_base + AT91_AIC5_ISCR);
139 	irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
140 	smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR);
143 		irq_reg_writel(smr, gc->reg_base + AT91_AIC5_SMR);
166 			       bgc->reg_base + AT91_AIC5_SSR);
168 			irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IECR);
170 			irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR);
191 			       bgc->reg_base + AT91_AIC5_SSR);
193 			irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IECR);
195 			irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR);
211 			       bgc->reg_base + AT91_AIC5_SSR);
212 		irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR);
213 		irq_reg_writel(1, bgc->reg_base + AT91_AIC5_ICCR);
233 		irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR);
240 	irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC5_SPU);
243 	irq_reg_writel(0, gc->reg_base + AT91_AIC5_DCR);
247 		irq_reg_writel(i, gc->reg_base + AT91_AIC5_SSR);
248 		irq_reg_writel(i, gc->reg_base + AT91_AIC5_SVR);
249 		irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR);
250 		irq_reg_writel(1, gc->reg_base + AT91_AIC5_ICCR);
276 	irq_reg_writel(*out_hwirq, gc->reg_base + AT91_AIC5_SSR);
277 	smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR);
280 		irq_reg_writel(intspec[2] | smr, gc->reg_base + AT91_AIC5_SMR);