Lines Matching defs:bcs
166 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
167 return (&cs->bcs[0]);
168 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
169 return (&cs->bcs[1]);
175 write_ctrl(struct BCState *bcs, int which) {
177 if (bcs->cs->debug & L1_DEB_HSCX)
178 debugl1(bcs->cs, "hdlc %c wr%x ctrl %x",
179 'A' + bcs->channel, which, bcs->hw.hdlc.ctrl.ctrl);
180 if (bcs->cs->subtyp == AVM_FRITZ_PCI) {
181 WriteHDLCPCI(bcs->cs, bcs->channel, HDLC_STATUS, bcs->hw.hdlc.ctrl.ctrl);
184 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS + 2,
185 bcs->hw.hdlc.ctrl.sr.mode);
187 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS + 1,
188 bcs->hw.hdlc.ctrl.sr.xml);
190 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS,
191 bcs->hw.hdlc.ctrl.sr.cmd);
196 modehdlc(struct BCState *bcs, int mode, int bc)
198 struct IsdnCardState *cs = bcs->cs;
199 int hdlc = bcs->channel;
203 'A' + hdlc, bcs->mode, mode, hdlc, bc);
204 bcs->hw.hdlc.ctrl.ctrl = 0;
207 bcs->mode = 1;
208 bcs->channel = bc;
211 if (bcs->mode == L1_MODE_NULL)
213 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
214 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_TRANS;
215 write_ctrl(bcs, 5);
216 bcs->mode = L1_MODE_NULL;
217 bcs->channel = bc;
220 bcs->mode = mode;
221 bcs->channel = bc;
222 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
223 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_TRANS;
224 write_ctrl(bcs, 5);
225 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS;
226 write_ctrl(bcs, 1);
227 bcs->hw.hdlc.ctrl.sr.cmd = 0;
228 schedule_event(bcs, B_XMTBUFREADY);
231 bcs->mode = mode;
232 bcs->channel = bc;
233 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
234 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_ITF_FLG;
235 write_ctrl(bcs, 5);
236 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS;
237 write_ctrl(bcs, 1);
238 bcs->hw.hdlc.ctrl.sr.cmd = 0;
239 schedule_event(bcs, B_XMTBUFREADY);
245 hdlc_empty_fifo(struct BCState *bcs, int count)
249 u_char idx = bcs->channel ? AVM_HDLC_2 : AVM_HDLC_1;
251 struct IsdnCardState *cs = bcs->cs;
255 if (bcs->hw.hdlc.rcvidx + count > HSCX_BUFMAX) {
260 p = bcs->hw.hdlc.rcvbuf + bcs->hw.hdlc.rcvidx;
262 bcs->hw.hdlc.rcvidx += count;
281 char *t = bcs->blog;
286 bcs->channel ? 'B' : 'A', count);
288 debugl1(cs, "%s", bcs->blog);
293 hdlc_fill_fifo(struct BCState *bcs)
295 struct IsdnCardState *cs = bcs->cs;
303 if (!bcs->tx_skb)
305 if (bcs->tx_skb->len <= 0)
308 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_XME;
309 if (bcs->tx_skb->len > fifo_size) {
312 count = bcs->tx_skb->len;
313 if (bcs->mode != L1_MODE_TRANS)
314 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_XME;
317 debugl1(cs, "hdlc_fill_fifo %d/%u", count, bcs->tx_skb->len);
318 p = bcs->tx_skb->data;
320 skb_pull(bcs->tx_skb, count);
321 bcs->tx_cnt -= count;
322 bcs->hw.hdlc.count += count;
323 bcs->hw.hdlc.ctrl.sr.xml = ((count == fifo_size) ? 0 : count);
324 write_ctrl(bcs, 3); /* sets the correct index too */
341 char *t = bcs->blog;
346 bcs->channel ? 'B' : 'A', count);
348 debugl1(cs, "%s", bcs->blog);
353 HDLC_irq(struct BCState *bcs, u_int stat) {
357 if (bcs->cs->debug & L1_DEB_HSCX)
358 debugl1(bcs->cs, "ch%d stat %#x", bcs->channel, stat);
361 if (bcs->cs->debug & L1_DEB_HSCX)
362 debugl1(bcs->cs, "RDO");
364 debugl1(bcs->cs, "ch%d stat %#x", bcs->channel, stat);
365 bcs->hw.hdlc.ctrl.sr.xml = 0;
366 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_RRS;
367 write_ctrl(bcs, 1);
368 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_RRS;
369 write_ctrl(bcs, 1);
370 bcs->hw.hdlc.rcvidx = 0;
374 hdlc_empty_fifo(bcs, len);
375 if ((stat & HDLC_STAT_RME) || (bcs->mode == L1_MODE_TRANS)) {
377 (bcs->mode == L1_MODE_TRANS)) {
378 if (!(skb = dev_alloc_skb(bcs->hw.hdlc.rcvidx)))
381 memcpy(skb_put(skb, bcs->hw.hdlc.rcvidx),
382 bcs->hw.hdlc.rcvbuf, bcs->hw.hdlc.rcvidx);
383 skb_queue_tail(&bcs->rqueue, skb);
385 bcs->hw.hdlc.rcvidx = 0;
386 schedule_event(bcs, B_RCVBUFREADY);
388 if (bcs->cs->debug & L1_DEB_HSCX)
389 debugl1(bcs->cs, "invalid frame");
391 debugl1(bcs->cs, "ch%d invalid frame %#x", bcs->channel, stat);
392 bcs->hw.hdlc.rcvidx = 0;
401 if (bcs->tx_skb) {
402 skb_push(bcs->tx_skb, bcs->hw.hdlc.count);
403 bcs->tx_cnt += bcs->hw.hdlc.count;
404 bcs->hw.hdlc.count = 0;
405 if (bcs->cs->debug & L1_DEB_WARN)
406 debugl1(bcs->cs, "ch%d XDU", bcs->channel);
407 } else if (bcs->cs->debug & L1_DEB_WARN)
408 debugl1(bcs->cs, "ch%d XDU without skb", bcs->channel);
409 bcs->hw.hdlc.ctrl.sr.xml = 0;
410 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_XRS;
411 write_ctrl(bcs, 1);
412 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_XRS;
413 write_ctrl(bcs, 1);
414 hdlc_fill_fifo(bcs);
416 if (bcs->tx_skb) {
417 if (bcs->tx_skb->len) {
418 hdlc_fill_fifo(bcs);
421 if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
422 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
424 spin_lock_irqsave(&bcs->aclock, flags);
425 bcs->ackcnt += bcs->hw.hdlc.count;
426 spin_unlock_irqrestore(&bcs->aclock, flags);
427 schedule_event(bcs, B_ACKPENDING);
429 dev_kfree_skb_irq(bcs->tx_skb);
430 bcs->hw.hdlc.count = 0;
431 bcs->tx_skb = NULL;
434 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
435 bcs->hw.hdlc.count = 0;
436 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
437 hdlc_fill_fifo(bcs);
439 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
440 schedule_event(bcs, B_XMTBUFREADY);
449 struct BCState *bcs;
459 if (!(bcs = Sel_BCS(cs, 0))) {
463 HDLC_irq(bcs, stat);
473 if (!(bcs = Sel_BCS(cs, 1))) {
477 HDLC_irq(bcs, stat);
484 struct BCState *bcs = st->l1.bcs;
490 spin_lock_irqsave(&bcs->cs->lock, flags);
491 if (bcs->tx_skb) {
492 skb_queue_tail(&bcs->squeue, skb);
494 bcs->tx_skb = skb;
495 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
496 bcs->hw.hdlc.count = 0;
497 bcs->cs->BC_Send_Data(bcs);
499 spin_unlock_irqrestore(&bcs->cs->lock, flags);
502 spin_lock_irqsave(&bcs->cs->lock, flags);
503 if (bcs->tx_skb) {
506 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
507 bcs->tx_skb = skb;
508 bcs->hw.hdlc.count = 0;
509 bcs->cs->BC_Send_Data(bcs);
511 spin_unlock_irqrestore(&bcs->cs->lock, flags);
514 if (!bcs->tx_skb) {
521 spin_lock_irqsave(&bcs->cs->lock, flags);
522 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
523 modehdlc(bcs, st->l1.mode, st->l1.bc);
524 spin_unlock_irqrestore(&bcs->cs->lock, flags);
531 spin_lock_irqsave(&bcs->cs->lock, flags);
532 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
533 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
534 modehdlc(bcs, 0, st->l1.bc);
535 spin_unlock_irqrestore(&bcs->cs->lock, flags);
542 close_hdlcstate(struct BCState *bcs)
544 modehdlc(bcs, 0, 0);
545 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
546 kfree(bcs->hw.hdlc.rcvbuf);
547 bcs->hw.hdlc.rcvbuf = NULL;
548 kfree(bcs->blog);
549 bcs->blog = NULL;
550 skb_queue_purge(&bcs->rqueue);
551 skb_queue_purge(&bcs->squeue);
552 if (bcs->tx_skb) {
553 dev_kfree_skb_any(bcs->tx_skb);
554 bcs->tx_skb = NULL;
555 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
561 open_hdlcstate(struct IsdnCardState *cs, struct BCState *bcs)
563 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
564 if (!(bcs->hw.hdlc.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
569 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
571 "HiSax: No memory for bcs->blog\n");
572 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
573 kfree(bcs->hw.hdlc.rcvbuf);
574 bcs->hw.hdlc.rcvbuf = NULL;
577 skb_queue_head_init(&bcs->rqueue);
578 skb_queue_head_init(&bcs->squeue);
580 bcs->tx_skb = NULL;
581 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
582 bcs->event = 0;
583 bcs->hw.hdlc.rcvidx = 0;
584 bcs->tx_cnt = 0;
589 setstack_hdlc(struct PStack *st, struct BCState *bcs)
591 bcs->channel = st->l1.bc;
592 if (open_hdlcstate(st->l1.hardware, bcs))
594 st->l1.bcs = bcs;
597 bcs->st = st;
637 cs->bcs[0].BC_SetStack = setstack_hdlc;
638 cs->bcs[1].BC_SetStack = setstack_hdlc;
639 cs->bcs[0].BC_Close = close_hdlcstate;
640 cs->bcs[1].BC_Close = close_hdlcstate;
641 modehdlc(cs->bcs, -1, 0);
642 modehdlc(cs->bcs + 1, -1, 1);