Cross Reference: /drivers/isdn/hisax/bkm

Lines Matching refs:ax
80 	return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80));
86 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value);
92 	readfifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);
98 	writefifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);
105 	return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0)));
111 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value);
119 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK,
127 #define READHSCX(cs, nr, reg) readreg(cs->hw.ax.base,			\
128 				      cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0))
129 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ax.base,		\
130 					      cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0), data)
131 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ax.base,		\
132 						cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
133 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ax.base,	\
134 						  cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
146 	ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);
155 		val = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, HSCX_ISTA + 0x40);
167 		val = 0xfe & readreg(cs->hw.ax.base, cs->hw.ax.data_adr, ISAC_ISTA | 0x80);
176 	ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);
184 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF);
185 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0);
193 	release_region(cs->hw.ax.base & 0xffffffc0, 128);
195 		release_region(cs->hw.ax.plx_adr, 64);
203 			wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) | 0x41));
205 			wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) & ~0x41));
213 		wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) & ~4));
216 		wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) | 4));
370 	cs->hw.ax.plx_adr = pci_ioaddr1;
374 		cs->hw.ax.base = pci_ioaddr5 + 0x00;
390 		cs->hw.ax.base = pci_ioaddr4 + 0x08;
395 		cs->hw.ax.base = pci_ioaddr3 + 0x10;
400 		cs->hw.ax.base = pci_ioaddr2 + 0x20;
406 	cs->hw.ax.data_adr = cs->hw.ax.base + 4;
411 	       cs->hw.ax.plx_adr,
412 	       cs->hw.ax.base,
413 	       cs->hw.ax.data_adr,
431 	       readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));