Cross Reference: /drivers/isdn/hisax/enternow

Lines Matching refs:njet
85  * From address hw.njet.base + TJ_AMD_PORT onwards, the AMD
87  * -> 0x01 of the AMD at hw.njet.base + 0C4 */
101 		return (inb(cs->hw.njet.isac + 4 * offset));
105 		outb(offset, cs->hw.njet.isac + 4 * AMD_CR);
106 		return (inb(cs->hw.njet.isac + 4 * AMD_DR));
116 		outb(value, cs->hw.njet.isac + 4 * offset);
120 		outb(offset, cs->hw.njet.isac + 4 * AMD_CR);
121 		outb(value, cs->hw.njet.isac + 4 * AMD_DR);
129 		outb(0x00, cs->hw.njet.base + NETJET_IRQMASK1);
131 		outb(TJ_AMD_IRQ, cs->hw.njet.base + NETJET_IRQMASK1);
156 	cs->hw.njet.ctrl_reg = 0x07;
157 	outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL);
160 	cs->hw.njet.ctrl_reg = 0x30;
161 	outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL);
164 	cs->hw.njet.auxd = 0;  // LED-status
165 	cs->hw.njet.dmactrl = 0;
166 	outb(~TJ_AMD_IRQ, cs->hw.njet.base + NETJET_AUXCTRL);
167 	outb(TJ_AMD_IRQ, cs->hw.njet.base + NETJET_IRQMASK1);
168 	outb(cs->hw.njet.auxd, cs->hw.njet.auxa); // LED off
201 		cs->hw.njet.auxd = TJ_AMD_IRQ << 1;
202 		outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA);
206 		cs->hw.njet.auxd = 0;
207 		outb(0x00, cs->hw.njet.base + NETJET_AUXDATA);
218 		cs->hw.njet.auxd |= TJ_AMD_IRQ << 2;
219 		outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA);
231 			cs->hw.njet.auxd &= ~(TJ_AMD_IRQ << 2);
232 			outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA);
250 	s1val = inb(cs->hw.njet.base + NETJET_IRQSTAT1);
260 	s0val = inb(cs->hw.njet.base + NETJET_IRQSTAT0);
266 		outb(s0val, cs->hw.njet.base + NETJET_IRQSTAT0);
270 	if (inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR) <
271 	    inl(cs->hw.njet.base + NETJET_DMA_WRITE_IRQ))
276 	if (inl(cs->hw.njet.base + NETJET_DMA_READ_ADR) <
277 	    inl(cs->hw.njet.base + NETJET_DMA_READ_IRQ))
282 	if (s0val != cs->hw.njet.last_is0) /* we have a DMA interrupt */
288 		cs->hw.njet.irqstat0 = s0val;
289 		if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_READ) !=
290 		    (cs->hw.njet.last_is0 & NETJET_IRQM0_READ))
293 		if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE) !=
294 		    (cs->hw.njet.last_is0 & NETJET_IRQM0_WRITE))
312 	cs->hw.njet.base = pci_resource_start(dev_netjet, 0);
313 	if (!cs->hw.njet.base) {
330 	cs->hw.njet.auxa = cs->hw.njet.base + NETJET_AUXDATA;
331 	cs->hw.njet.isac = cs->hw.njet.base + 0xC0; // Fenster zum AMD
334 	cs->hw.njet.ctrl_reg = 0x07;  // geändert von 0xff
335 	outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL);
339 	cs->hw.njet.ctrl_reg = 0x30;  /* Reset Off and status read clear */
340 	outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL);
343 	cs->hw.njet.auxd = 0x00; // war 0xc0
344 	cs->hw.njet.dmactrl = 0;
346 	outb(~TJ_AMD_IRQ, cs->hw.njet.base + NETJET_AUXCTRL);
347 	outb(TJ_AMD_IRQ, cs->hw.njet.base + NETJET_IRQMASK1);
348 	outb(cs->hw.njet.auxd, cs->hw.njet.auxa);
357 	       cs->hw.njet.base, cs->irq);
358 	if (!request_region(cs->hw.njet.base, bytecnt, "Fn_ISDN")) {
361 		       cs->hw.njet.base,
362 		       cs->hw.njet.base + bytecnt);
367 	cs->hw.njet.last_is0 = 0;