Cross Reference: /drivers/isdn/hisax/hfc

Lines Matching defs:bcs
143 GetFreeFifoBytes_B(struct BCState *bcs)
147 	if (bcs->hw.hfc.f1 == bcs->hw.hfc.f2)
148 		return (bcs->cs->hw.hfcD.bfifosize);
149 	s = bcs->hw.hfc.send[bcs->hw.hfc.f1] - bcs->hw.hfc.send[bcs->hw.hfc.f2];
151 		s += bcs->cs->hw.hfcD.bfifosize;
152 	s = bcs->cs->hw.hfcD.bfifosize - s;
183 *hfc_empty_fifo(struct BCState *bcs, int count)
187 	struct IsdnCardState *cs = bcs->cs;
198 		cip = HFCB_FIFO | HFCB_FIFO_OUT | HFCB_REC | HFCB_CHANNEL(bcs->channel);
207 		cip = HFCB_FIFO | HFCB_FIFO_OUT | HFCB_REC | HFCB_CHANNEL(bcs->channel);
209 		bcs->err_inv++;
219 		cip = HFCB_FIFO | HFCB_FIFO_OUT | HFCB_REC | HFCB_CHANNEL(bcs->channel);
229 			printk(KERN_WARNING "HFC FIFO channel %d BUSY Error\n", bcs->channel);
241 					bcs->channel, chksum, stat);
247 				bcs->err_crc++;
255 		       HFCB_REC | HFCB_CHANNEL(bcs->channel));
261 hfc_fill_fifo(struct BCState *bcs)
263 	struct IsdnCardState *cs = bcs->cs;
268 	if (!bcs->tx_skb)
270 	if (bcs->tx_skb->len <= 0)
272 	SelFiFo(cs, HFCB_SEND | HFCB_CHANNEL(bcs->channel));
273 	cip = HFCB_FIFO | HFCB_F1 | HFCB_SEND | HFCB_CHANNEL(bcs->channel);
275 	bcs->hw.hfc.f1 = ReadReg(cs, HFCD_DATA, cip);
277 	cip = HFCB_FIFO | HFCB_F2 | HFCB_SEND | HFCB_CHANNEL(bcs->channel);
279 	bcs->hw.hfc.f2 = ReadReg(cs, HFCD_DATA, cip);
280 	bcs->hw.hfc.send[bcs->hw.hfc.f1] = ReadZReg(cs, HFCB_FIFO | HFCB_Z1 | HFCB_SEND | HFCB_CHANNEL(bcs->channel));
283 			bcs->channel, bcs->hw.hfc.f1, bcs->hw.hfc.f2,
284 			bcs->hw.hfc.send[bcs->hw.hfc.f1]);
285 	fcnt = bcs->hw.hfc.f1 - bcs->hw.hfc.f2;
293 	count = GetFreeFifoBytes_B(bcs);
296 			bcs->channel, bcs->tx_skb->len,
298 	if (count < bcs->tx_skb->len) {
303 	cip = HFCB_FIFO | HFCB_FIFO_IN | HFCB_SEND | HFCB_CHANNEL(bcs->channel);
307 	WriteReg(cs, HFCD_DATA_NODEB, cip, bcs->tx_skb->data[idx++]);
308 	while (idx < bcs->tx_skb->len) {
311 		WriteReg(cs, HFCD_DATA_NODEB, cip, bcs->tx_skb->data[idx]);
314 	if (idx != bcs->tx_skb->len) {
316 		printk(KERN_WARNING "HFC S FIFO channel %d BUSY Error\n", bcs->channel);
318 		bcs->tx_cnt -= bcs->tx_skb->len;
319 		if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
320 		    (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
322 			spin_lock_irqsave(&bcs->aclock, flags);
323 			bcs->ackcnt += bcs->tx_skb->len;
324 			spin_unlock_irqrestore(&bcs->aclock, flags);
325 			schedule_event(bcs, B_ACKPENDING);
327 		dev_kfree_skb_any(bcs->tx_skb);
328 		bcs->tx_skb = NULL;
332 	ReadReg(cs, HFCD_DATA, HFCB_FIFO | HFCB_F1_INC | HFCB_SEND | HFCB_CHANNEL(bcs->channel));
334 	test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
339 hfc_send_data(struct BCState *bcs)
341 	struct IsdnCardState *cs = bcs->cs;
344 		hfc_fill_fifo(bcs);
347 		debugl1(cs, "send_data %d blocked", bcs->channel);
351 main_rec_2bds0(struct BCState *bcs)
353 	struct IsdnCardState *cs = bcs->cs;
362 		debugl1(cs, "rec_data %d blocked", bcs->channel);
365 	SelFiFo(cs, HFCB_REC | HFCB_CHANNEL(bcs->channel));
366 	cip = HFCB_FIFO | HFCB_F1 | HFCB_REC | HFCB_CHANNEL(bcs->channel);
369 	cip = HFCB_FIFO | HFCB_F2 | HFCB_REC | HFCB_CHANNEL(bcs->channel);
375 				bcs->channel, f1, f2);
376 		z1 = ReadZReg(cs, HFCB_FIFO | HFCB_Z1 | HFCB_REC | HFCB_CHANNEL(bcs->channel));
377 		z2 = ReadZReg(cs, HFCB_FIFO | HFCB_Z2 | HFCB_REC | HFCB_CHANNEL(bcs->channel));
384 				bcs->channel, z1, z2, rcnt);
385 		if ((skb = hfc_empty_fifo(bcs, rcnt))) {
386 			skb_queue_tail(&bcs->rqueue, skb);
387 			schedule_event(bcs, B_RCVBUFREADY);
405 mode_2bs0(struct BCState *bcs, int mode, int bc)
407 	struct IsdnCardState *cs = bcs->cs;
411 			mode, bc, bcs->channel);
412 	bcs->mode = mode;
413 	bcs->channel = bc;
455 	struct BCState *bcs = st->l1.bcs;
461 		spin_lock_irqsave(&bcs->cs->lock, flags);
462 		if (bcs->tx_skb) {
463 			skb_queue_tail(&bcs->squeue, skb);
465 			bcs->tx_skb = skb;
466 //				test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
467 			bcs->cs->BC_Send_Data(bcs);
469 		spin_unlock_irqrestore(&bcs->cs->lock, flags);
472 		spin_lock_irqsave(&bcs->cs->lock, flags);
473 		if (bcs->tx_skb) {
476 //				test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
477 			bcs->tx_skb = skb;
478 			bcs->cs->BC_Send_Data(bcs);
480 		spin_unlock_irqrestore(&bcs->cs->lock, flags);
483 		if (!bcs->tx_skb) {
490 		spin_lock_irqsave(&bcs->cs->lock, flags);
491 		test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
492 		mode_2bs0(bcs, st->l1.mode, st->l1.bc);
493 		spin_unlock_irqrestore(&bcs->cs->lock, flags);
500 		spin_lock_irqsave(&bcs->cs->lock, flags);
501 		test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
502 		test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
503 		mode_2bs0(bcs, 0, st->l1.bc);
504 		spin_unlock_irqrestore(&bcs->cs->lock, flags);
511 close_2bs0(struct BCState *bcs)
513 	mode_2bs0(bcs, 0, bcs->channel);
514 	if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
515 		skb_queue_purge(&bcs->rqueue);
516 		skb_queue_purge(&bcs->squeue);
517 		if (bcs->tx_skb) {
518 			dev_kfree_skb_any(bcs->tx_skb);
519 			bcs->tx_skb = NULL;
520 			test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
526 open_hfcstate(struct IsdnCardState *cs, struct BCState *bcs)
528 	if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
529 		skb_queue_head_init(&bcs->rqueue);
530 		skb_queue_head_init(&bcs->squeue);
532 	bcs->tx_skb = NULL;
533 	test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
534 	bcs->event = 0;
535 	bcs->tx_cnt = 0;
540 setstack_2b(struct PStack *st, struct BCState *bcs)
542 	bcs->channel = st->l1.bc;
543 	if (open_hfcstate(st->l1.hardware, bcs))
545 	st->l1.bcs = bcs;
548 	bcs->st = st;
756 	if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
757 		return (&cs->bcs[0]);
758 	else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
759 		return (&cs->bcs[1]);
768 	struct BCState *bcs;
796 			if (!(bcs = Sel_BCS(cs, 0))) {
800 				main_rec_2bds0(bcs);
803 			if (!(bcs = Sel_BCS(cs, 1))) {
807 				main_rec_2bds0(bcs);
810 			if (!(bcs = Sel_BCS(cs, 0))) {
814 				if (bcs->tx_skb) {
816 						hfc_fill_fifo(bcs);
819 						debugl1(cs, "fill_data %d blocked", bcs->channel);
821 					if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
823 							hfc_fill_fifo(bcs);
826 							debugl1(cs, "fill_data %d blocked", bcs->channel);
828 						schedule_event(bcs, B_XMTBUFREADY);
834 			if (!(bcs = Sel_BCS(cs, 1))) {
838 				if (bcs->tx_skb) {
840 						hfc_fill_fifo(bcs);
843 						debugl1(cs, "fill_data %d blocked", bcs->channel);
845 					if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
847 							hfc_fill_fifo(bcs);
850 							debugl1(cs, "fill_data %d blocked", bcs->channel);
852 						schedule_event(bcs, B_XMTBUFREADY);
1043 	if (!cs->bcs[0].hw.hfc.send)
1044 		cs->bcs[0].hw.hfc.send = init_send_hfcd(32);
1045 	if (!cs->bcs[1].hw.hfc.send)
1046 		cs->bcs[1].hw.hfc.send = init_send_hfcd(32);
1048 	cs->bcs[0].BC_SetStack = setstack_2b;
1049 	cs->bcs[1].BC_SetStack = setstack_2b;
1050 	cs->bcs[0].BC_Close = close_2bs0;
1051 	cs->bcs[1].BC_Close = close_2bs0;
1052 	mode_2bs0(cs->bcs, 0, 0);
1053 	mode_2bs0(cs->bcs + 1, 0, 1);
1059 	kfree(cs->bcs[0].hw.hfc.send);
1060 	cs->bcs[0].hw.hfc.send = NULL;
1061 	kfree(cs->bcs[1].hw.hfc.send);
1062 	cs->bcs[1].hw.hfc.send = NULL;