Cross Reference: /drivers/isdn/hisax/hfc

Lines Matching defs:bcs
57 GetFreeFifoBytes(struct BCState *bcs)
61 	if (bcs->hw.hfc.f1 == bcs->hw.hfc.f2)
62 		return (bcs->cs->hw.hfc.fifosize);
63 	s = bcs->hw.hfc.send[bcs->hw.hfc.f1] - bcs->hw.hfc.send[bcs->hw.hfc.f2];
65 		s += bcs->cs->hw.hfc.fifosize;
66 	s = bcs->cs->hw.hfc.fifosize - s;
71 ReadZReg(struct BCState *bcs, u_char reg)
75 	WaitNoBusy(bcs->cs);
76 	val = 256 * bcs->cs->BC_Read_Reg(bcs->cs, HFC_DATA, reg | HFC_CIP | HFC_Z_HIGH);
77 	WaitNoBusy(bcs->cs);
78 	val += bcs->cs->BC_Read_Reg(bcs->cs, HFC_DATA, reg | HFC_CIP | HFC_Z_LOW);
83 hfc_clear_fifo(struct BCState *bcs)
85 	struct IsdnCardState *cs = bcs->cs;
92 	cip = HFC_CIP | HFC_F1 | HFC_REC | HFC_CHANNEL(bcs->channel);
99 	cip = HFC_CIP | HFC_F2 | HFC_REC | HFC_CHANNEL(bcs->channel);
102 	z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
103 	z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
108 				bcs->channel, f1, f2);
116 				bcs->channel, z1, z2, rcnt);
117 		cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
126 					HFC_CHANNEL(bcs->channel));
129 		cip = HFC_CIP | HFC_F1 | HFC_REC | HFC_CHANNEL(bcs->channel);
132 		cip = HFC_CIP | HFC_F2 | HFC_REC | HFC_CHANNEL(bcs->channel);
135 		z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
136 		z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
144 hfc_empty_fifo(struct BCState *bcs, int count)
148 	struct IsdnCardState *cs = bcs->cs;
159 		cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
164 				       HFC_CHANNEL(bcs->channel));
168 	if ((count < 4) && (bcs->mode != L1_MODE_TRANS)) {
171 		cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
176 				       HFC_CHANNEL(bcs->channel));
179 		bcs->err_inv++;
183 	if (bcs->mode == L1_MODE_TRANS)
192 		cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
199 			printk(KERN_WARNING "HFC FIFO channel %d BUSY Error\n", bcs->channel);
201 			if (bcs->mode != L1_MODE_TRANS) {
204 						       HFC_CHANNEL(bcs->channel));
209 		if (bcs->mode != L1_MODE_TRANS) {
218 					bcs->channel, chksum, stat);
224 				bcs->err_crc++;
229 					       HFC_CHANNEL(bcs->channel));
237 hfc_fill_fifo(struct BCState *bcs)
239 	struct IsdnCardState *cs = bcs->cs;
245 	if (!bcs->tx_skb)
247 	if (bcs->tx_skb->len <= 0)
250 	cip = HFC_CIP | HFC_F1 | HFC_SEND | HFC_CHANNEL(bcs->channel);
256 	if (bcs->mode != L1_MODE_TRANS) {
257 		bcs->hw.hfc.f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
258 		cip = HFC_CIP | HFC_F2 | HFC_SEND | HFC_CHANNEL(bcs->channel);
260 		bcs->hw.hfc.f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
261 		bcs->hw.hfc.send[bcs->hw.hfc.f1] = ReadZReg(bcs, HFC_Z1 | HFC_SEND | HFC_CHANNEL(bcs->channel));
264 				bcs->channel, bcs->hw.hfc.f1, bcs->hw.hfc.f2,
265 				bcs->hw.hfc.send[bcs->hw.hfc.f1]);
266 		fcnt = bcs->hw.hfc.f1 - bcs->hw.hfc.f2;
274 		count = GetFreeFifoBytes(bcs);
278 		z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
279 		z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
286 			bcs->channel, bcs->tx_skb->len,
288 	if (count < bcs->tx_skb->len) {
293 	cip = HFC_CIP | HFC_FIFO_IN | HFC_SEND | HFC_CHANNEL(bcs->channel);
295 	while ((idx < bcs->tx_skb->len) && WaitNoBusy(cs))
296 		cs->BC_Write_Reg(cs, HFC_DATA_NODEB, cip, bcs->tx_skb->data[idx++]);
297 	if (idx != bcs->tx_skb->len) {
299 		printk(KERN_WARNING "HFC S FIFO channel %d BUSY Error\n", bcs->channel);
301 		count =  bcs->tx_skb->len;
302 		bcs->tx_cnt -= count;
303 		if (PACKET_NOACK == bcs->tx_skb->pkt_type)
305 		dev_kfree_skb_any(bcs->tx_skb);
306 		bcs->tx_skb = NULL;
307 		if (bcs->mode != L1_MODE_TRANS) {
310 			cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F1_INC | HFC_SEND | HFC_CHANNEL(bcs->channel));
312 		if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
315 			spin_lock_irqsave(&bcs->aclock, flags);
316 			bcs->ackcnt += count;
317 			spin_unlock_irqrestore(&bcs->aclock, flags);
318 			schedule_event(bcs, B_ACKPENDING);
320 		test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
326 main_irq_hfc(struct BCState *bcs)
328 	struct IsdnCardState *cs = bcs->cs;
336 	cip = HFC_CIP | HFC_F1 | HFC_REC | HFC_CHANNEL(bcs->channel);
343 	if (bcs->mode == L1_MODE_HDLC) {
345 		cip = HFC_CIP | HFC_F2 | HFC_REC | HFC_CHANNEL(bcs->channel);
351 					bcs->channel, f1, f2);
355 	if (receive || (bcs->mode == L1_MODE_TRANS)) {
357 		z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
358 		z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
362 		if ((bcs->mode == L1_MODE_HDLC) || (rcnt)) {
366 					bcs->channel, z1, z2, rcnt);
368 			if ((skb = hfc_empty_fifo(bcs, rcnt))) {
369 				skb_queue_tail(&bcs->rqueue, skb);
370 				schedule_event(bcs, B_RCVBUFREADY);
375 	if (bcs->tx_skb) {
377 		test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
378 		hfc_fill_fifo(bcs);
379 		if (test_bit(BC_FLG_BUSY, &bcs->Flag))
382 		if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
384 			test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
385 			hfc_fill_fifo(bcs);
386 			if (test_bit(BC_FLG_BUSY, &bcs->Flag))
390 			schedule_event(bcs, B_XMTBUFREADY);
399 mode_hfc(struct BCState *bcs, int mode, int bc)
401 	struct IsdnCardState *cs = bcs->cs;
405 			mode, bc, bcs->channel);
406 	bcs->mode = mode;
407 	bcs->channel = bc;
423 		hfc_clear_fifo(bcs); /* complete fifo clear */
449 		hfc_clear_fifo(bcs);
455 	struct BCState	*bcs = st->l1.bcs;
461 		spin_lock_irqsave(&bcs->cs->lock, flags);
462 		if (bcs->tx_skb) {
463 			skb_queue_tail(&bcs->squeue, skb);
465 			bcs->tx_skb = skb;
466 			test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
467 			bcs->cs->BC_Send_Data(bcs);
469 		spin_unlock_irqrestore(&bcs->cs->lock, flags);
472 		spin_lock_irqsave(&bcs->cs->lock, flags);
473 		if (bcs->tx_skb) {
476 			test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
477 			bcs->tx_skb = skb;
478 			bcs->cs->BC_Send_Data(bcs);
480 		spin_unlock_irqrestore(&bcs->cs->lock, flags);
483 		if (!bcs->tx_skb) {
490 		spin_lock_irqsave(&bcs->cs->lock, flags);
491 		test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
492 		mode_hfc(bcs, st->l1.mode, st->l1.bc);
493 		spin_unlock_irqrestore(&bcs->cs->lock, flags);
500 		spin_lock_irqsave(&bcs->cs->lock, flags);
501 		test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
502 		test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
503 		mode_hfc(bcs, 0, st->l1.bc);
504 		spin_unlock_irqrestore(&bcs->cs->lock, flags);
512 close_hfcstate(struct BCState *bcs)
514 	mode_hfc(bcs, 0, bcs->channel);
515 	if (test_bit(BC_FLG_INIT, &bcs->Flag)) {
516 		skb_queue_purge(&bcs->rqueue);
517 		skb_queue_purge(&bcs->squeue);
518 		if (bcs->tx_skb) {
519 			dev_kfree_skb_any(bcs->tx_skb);
520 			bcs->tx_skb = NULL;
521 			test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
524 	test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
528 open_hfcstate(struct IsdnCardState *cs, struct BCState *bcs)
530 	if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
531 		skb_queue_head_init(&bcs->rqueue);
532 		skb_queue_head_init(&bcs->squeue);
534 	bcs->tx_skb = NULL;
535 	test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
536 	bcs->event = 0;
537 	bcs->tx_cnt = 0;
542 setstack_hfc(struct PStack *st, struct BCState *bcs)
544 	bcs->channel = st->l1.bc;
545 	if (open_hfcstate(st->l1.hardware, bcs))
547 	st->l1.bcs = bcs;
550 	bcs->st = st;
556 init_send(struct BCState *bcs)
560 	if (!(bcs->hw.hfc.send = kmalloc(32 * sizeof(unsigned int), GFP_ATOMIC))) {
566 		bcs->hw.hfc.send[i] = 0x1fff;
572 	init_send(&cs->bcs[0]);
573 	init_send(&cs->bcs[1]);
575 	cs->bcs[0].BC_SetStack = setstack_hfc;
576 	cs->bcs[1].BC_SetStack = setstack_hfc;
577 	cs->bcs[0].BC_Close = close_hfcstate;
578 	cs->bcs[1].BC_Close = close_hfcstate;
579 	mode_hfc(cs->bcs, 0, 0);
580 	mode_hfc(cs->bcs + 1, 0, 0);
586 	kfree(cs->bcs[0].hw.hfc.send);
587 	cs->bcs[0].hw.hfc.send = NULL;
588 	kfree(cs->bcs[1].hw.hfc.send);
589 	cs->bcs[1].hw.hfc.send = NULL;