Lines Matching refs:hfcpci
75 printk(KERN_INFO "HiSax: release hfcpci at %p\n",
76 cs->hw.hfcpci.pci_io);
77 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */
78 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
83 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
84 pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, 0); /* disable memory mapped ports + busmaster */
85 del_timer(&cs->hw.hfcpci.timer);
86 pci_free_consistent(cs->hw.hfcpci.dev, 0x8000,
87 cs->hw.hfcpci.fifos, cs->hw.hfcpci.dma);
88 cs->hw.hfcpci.fifos = NULL;
89 iounmap((void *)cs->hw.hfcpci.pci_io);
99 pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped ports, disable busmaster */
100 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */
101 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
104 pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO + PCI_ENA_MASTER); /* enable memory ports + busmaster */
112 cs->hw.hfcpci.fifo_en = 0x30; /* only D fifos enabled */
113 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
115 cs->hw.hfcpci.trm = 0 + HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
116 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
119 cs->hw.hfcpci.sctrl_e = HFCPCI_AUTO_AWAKE;
120 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); /* S/T Auto awake */
121 cs->hw.hfcpci.bswapped = 0; /* no exchange */
122 cs->hw.hfcpci.nt_mode = 0; /* we are in TE mode */
123 cs->hw.hfcpci.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
124 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
126 cs->hw.hfcpci.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
128 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
136 cs->hw.hfcpci.mst_m = HFCPCI_MASTER; /* HFC Master Mode */
138 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
139 cs->hw.hfcpci.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
140 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
141 cs->hw.hfcpci.sctrl_r = 0;
142 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
151 cs->hw.hfcpci.conn = 0x36; /* set data flow directions */
152 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
159 cs->hw.hfcpci.int_m2 = HFCPCI_IRQ_ENABLE;
160 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
170 cs->hw.hfcpci.timer.expires = jiffies + 75;
172 /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcpci.ctmt | 0x80);
173 add_timer(&cs->hw.hfcpci.timer);
221 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
222 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2RX;
224 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1;
225 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1RX;
228 cs->hw.hfcpci.fifo_en ^= fifo_state;
229 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
230 cs->hw.hfcpci.last_bfifo_cnt[fifo] = 0;
236 cs->hw.hfcpci.fifo_en |= fifo_state;
237 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
248 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2;
249 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2TX;
251 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1;
252 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1TX;
255 cs->hw.hfcpci.fifo_en ^= fifo_state;
256 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
262 cs->hw.hfcpci.fifo_en |= fifo_state;
263 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
339 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_rx;
351 debugl1(cs, "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)",
357 debugl1(cs, "empty_fifo hfcpci packet inv. len %d or crc %d", rcnt, df->data[zp->z1]);
461 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) {
462 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
463 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2;
466 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1;
467 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b1;
478 debugl1(cs, "hfcpci rec %d f1(%d) f2(%d)",
487 debugl1(cs, "hfcpci rec %d z1(%x) z2(%x) cnt(%d)",
496 if (cs->hw.hfcpci.last_bfifo_cnt[real_fifo] > rcnt + 1) {
500 cs->hw.hfcpci.last_bfifo_cnt[real_fifo] = rcnt;
530 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_tx;
603 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) {
604 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2;
605 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b2;
607 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1;
608 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b1;
775 (!(cs->hw.hfcpci.int_m1 & (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC + HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC)))) {
780 cs->hw.hfcpci.sctrl |= SCTRL_MODE_NT;
781 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); /* set NT-mode */
786 cs->dc.hfcpci.ph_state = 1;
787 cs->hw.hfcpci.nt_mode = 1;
788 cs->hw.hfcpci.nt_timer = 0;
794 if ((cs->chanlimit > 1) || (cs->hw.hfcpci.bswapped) ||
795 (cs->hw.hfcpci.nt_mode) || (ic->arg != 12))
801 cs->hw.hfcpci.trm |= 0x20; /* enable echo chan */
802 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_B2REC;
803 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2RX;
806 cs->hw.hfcpci.trm &= ~0x20; /* disable echo chan */
807 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_B2REC;
808 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2RX;
810 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA;
811 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA;
812 cs->hw.hfcpci.conn |= 0x10; /* B2-IOM -> B2-ST */
813 cs->hw.hfcpci.ctmt &= ~2;
814 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
815 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
816 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
817 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
818 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
819 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
820 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
840 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
841 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2;
850 debugl1(cs, "hfcpci e_rec f1(%d) f2(%d)",
859 debugl1(cs, "hfcpci e_rec z1(%x) z2(%x) cnt(%d)",
937 if (!(cs->hw.hfcpci.int_m2 & 0x08)) {
938 debugl1(cs, "HFC-PCI: int_m2 %x not initialised", cs->hw.hfcpci.int_m2);
954 val &= cs->hw.hfcpci.int_m1;
958 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcpci.ph_state,
960 cs->dc.hfcpci.ph_state = exval;
965 if (cs->hw.hfcpci.nt_mode) {
966 if ((--cs->hw.hfcpci.nt_timer) < 0)
970 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
974 cs->hw.hfcpci.int_s1 |= val;
978 if (cs->hw.hfcpci.int_s1 & 0x18) {
980 val = cs->hw.hfcpci.int_s1;
981 cs->hw.hfcpci.int_s1 = exval;
984 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) {
986 debugl1(cs, "hfcpci spurious 0x08 IRQ");
995 debugl1(cs, "hfcpci spurious 0x10 IRQ");
1000 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) {
1002 debugl1(cs, "hfcpci spurious 0x01 IRQ");
1026 debugl1(cs, "hfcpci spurious 0x02 IRQ");
1082 if (cs->hw.hfcpci.int_s1 && count--) {
1083 val = cs->hw.hfcpci.int_s1;
1084 cs->hw.hfcpci.int_s1 = 0;
1183 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
1184 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1196 cs->hw.hfcpci.mst_m &= ~HFCPCI_MASTER;
1197 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1202 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
1203 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1212 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~7) | 1;
1213 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1219 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~0x38) | 0x08;
1220 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1229 cs->hw.hfcpci.trm |= 0x80; /* enable IOM-loop */
1230 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
1280 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
1281 cs->hw.hfcpci.sctrl_e &= ~0x80;
1285 cs->hw.hfcpci.bswapped = 1; /* B1 and B2 exchanged */
1286 cs->hw.hfcpci.sctrl_e |= 0x80;
1288 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
1289 cs->hw.hfcpci.sctrl_e &= ~0x80;
1293 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
1294 cs->hw.hfcpci.sctrl_e &= ~0x80;
1300 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA;
1301 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA;
1303 cs->hw.hfcpci.sctrl &= ~SCTRL_B1_ENA;
1304 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B1_ENA;
1307 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
1308 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1310 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
1311 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1318 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1319 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1321 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1322 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1325 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
1326 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1327 cs->hw.hfcpci.ctmt |= 2;
1328 cs->hw.hfcpci.conn &= ~0x18;
1330 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
1331 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1332 cs->hw.hfcpci.ctmt |= 1;
1333 cs->hw.hfcpci.conn &= ~0x03;
1340 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1341 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1343 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1344 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1347 cs->hw.hfcpci.last_bfifo_cnt[1] = 0;
1348 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
1349 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1350 cs->hw.hfcpci.ctmt &= ~2;
1351 cs->hw.hfcpci.conn &= ~0x18;
1353 cs->hw.hfcpci.last_bfifo_cnt[0] = 0;
1354 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
1355 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1356 cs->hw.hfcpci.ctmt &= ~1;
1357 cs->hw.hfcpci.conn &= ~0x03;
1362 cs->hw.hfcpci.conn |= 0x10;
1363 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1364 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1365 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
1366 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1368 cs->hw.hfcpci.conn |= 0x02;
1369 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1370 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1371 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
1372 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1376 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e);
1377 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1378 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
1379 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
1380 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
1381 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
1382 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1511 if (!cs->hw.hfcpci.nt_mode)
1512 switch (cs->dc.hfcpci.ph_state) {
1532 switch (cs->dc.hfcpci.ph_state) {
1534 if (cs->hw.hfcpci.nt_timer < 0) {
1535 cs->hw.hfcpci.nt_timer = 0;
1536 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1537 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1543 cs->dc.hfcpci.ph_state = 4;
1545 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_TIMER;
1546 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1547 cs->hw.hfcpci.ctmt &= ~HFCPCI_AUTO_TIMER;
1548 cs->hw.hfcpci.ctmt |= HFCPCI_TIM3_125;
1549 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1550 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1551 cs->hw.hfcpci.nt_timer = NT_T1_COUNT;
1558 cs->hw.hfcpci.nt_timer = 0;
1559 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1560 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1621 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1622 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1624 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1649 cs->hw.hfcpci.int_s1 = 0;
1650 cs->dc.hfcpci.ph_state = 0;
1651 cs->hw.hfcpci.fifo = 255;
1690 cs->hw.hfcpci.dev = dev_hfcpci;
1696 cs->hw.hfcpci.pci_io = (char *)(unsigned long)dev_hfcpci->resource[1].start;
1699 if (!cs->hw.hfcpci.pci_io) {
1705 cs->hw.hfcpci.fifos = pci_alloc_consistent(cs->hw.hfcpci.dev,
1706 0x8000, &cs->hw.hfcpci.dma);
1707 if (!cs->hw.hfcpci.fifos) {
1711 if (cs->hw.hfcpci.dma & 0x7fff) {
1714 (u_long)cs->hw.hfcpci.dma);
1715 pci_free_consistent(cs->hw.hfcpci.dev, 0x8000,
1716 cs->hw.hfcpci.fifos, cs->hw.hfcpci.dma);
1719 pci_write_config_dword(cs->hw.hfcpci.dev, 0x80, (u32)cs->hw.hfcpci.dma);
1720 cs->hw.hfcpci.pci_io = ioremap((ulong) cs->hw.hfcpci.pci_io, 256);
1723 cs->hw.hfcpci.pci_io,
1724 cs->hw.hfcpci.fifos,
1725 (u_long)cs->hw.hfcpci.dma,
1730 pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped ports, disable busmaster */
1731 cs->hw.hfcpci.int_m2 = 0; /* disable alle interrupts */
1732 cs->hw.hfcpci.int_m1 = 0;
1733 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1734 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
1749 cs->hw.hfcpci.timer.function = (void *) hfcpci_Timer;
1750 cs->hw.hfcpci.timer.data = (long) cs;
1751 init_timer(&cs->hw.hfcpci.timer);