Lines Matching refs:cs
35 static void ph_command(struct IsdnCardState *cs, unsigned int command);
36 static inline void cic_int(struct IsdnCardState *cs);
38 static void dbusy_timer_handler(struct IsdnCardState *cs);
39 static void dch_empty_fifo(struct IsdnCardState *cs, int count);
40 static void dch_fill_fifo(struct IsdnCardState *cs);
41 static inline void dch_int(struct IsdnCardState *cs);
42 static void dch_setstack(struct PStack *st, struct IsdnCardState *cs);
43 static void dch_init(struct IsdnCardState *cs);
47 static void bch_int(struct IsdnCardState *cs, u_char hscx);
50 static int bch_open_state(struct IsdnCardState *cs, struct BCState *bcs);
52 static void bch_init(struct IsdnCardState *cs, int hscx);
53 static void clear_pending_ints(struct IsdnCardState *cs);
59 ph_command(struct IsdnCardState *cs, unsigned int command)
61 if (cs->debug & L1_DEB_ISAC)
62 debugl1(cs, "ph_command (%#x) in (%#x)", command,
63 cs->dc.isac.ph_state);
67 cs->writeisac(cs, IPACX_CIX0, (command << 4) | 0x0E);
74 cic_int(struct IsdnCardState *cs)
78 event = cs->readisac(cs, IPACX_CIR0) >> 4;
79 if (cs->debug & L1_DEB_ISAC) debugl1(cs, "cic_int(event=%#x)", event);
83 cs->dc.isac.ph_state = event;
84 schedule_event(cs, D_L1STATECHANGE);
97 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
103 if (cs->debug & DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len);
104 if (cs->debug & DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0);
105 if (cs->tx_skb) {
106 skb_queue_tail(&cs->sq, skb);
108 if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA Queued", 0);
111 cs->tx_skb = skb;
112 cs->tx_cnt = 0;
114 if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA", 0);
116 dch_fill_fifo(cs);
121 if (cs->tx_skb) {
122 if (cs->debug & L1_DEB_WARN)
123 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
124 skb_queue_tail(&cs->sq, skb);
127 if (cs->debug & DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len);
128 if (cs->debug & DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0);
129 cs->tx_skb = skb;
130 cs->tx_cnt = 0;
132 if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
134 dch_fill_fifo(cs);
139 if (cs->debug & L1_DEB_LAPD) debugl1(cs, "-> PH_REQUEST_PULL");
141 if (!cs->tx_skb) {
150 if ((cs->dc.isac.ph_state == IPACX_IND_RES) ||
151 (cs->dc.isac.ph_state == IPACX_IND_DR) ||
152 (cs->dc.isac.ph_state == IPACX_IND_DC))
153 ph_command(cs, IPACX_CMD_TIM);
155 ph_command(cs, IPACX_CMD_RES);
159 ph_command(cs, IPACX_CMD_AR8);
163 cs->writeisac(cs, IPACX_CDA_TSDP10, 0x80); // Timeslot 0 is B1
164 cs->writeisac(cs, IPACX_CDA_TSDP11, 0x81); // Timeslot 0 is B1
165 cda1_cr = cs->readisac(cs, IPACX_CDA1_CR);
166 (void) cs->readisac(cs, IPACX_CDA2_CR);
168 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr | 0x0a);
171 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr & ~0x0a);
174 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr | 0x14);
177 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr & ~0x14);
182 skb_queue_purge(&cs->rq);
183 skb_queue_purge(&cs->sq);
184 if (cs->tx_skb) {
185 dev_kfree_skb_any(cs->tx_skb);
186 cs->tx_skb = NULL;
188 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
189 del_timer(&cs->dbusytimer);
193 if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_l2l1 unknown %04x", pr);
201 dbusy_timer_handler(struct IsdnCardState *cs)
206 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
207 rbchd = cs->readisac(cs, IPACX_RBCHD);
208 stard = cs->readisac(cs, IPACX_STARD);
209 if (cs->debug)
210 debugl1(cs, "D-Channel Busy RBCHD %02x STARD %02x", rbchd, stard);
212 set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
213 for (st = cs->stlist; st; st = st->next) {
218 clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags);
219 if (cs->tx_skb) {
220 dev_kfree_skb_any(cs->tx_skb);
221 cs->tx_cnt = 0;
222 cs->tx_skb = NULL;
225 debugl1(cs, "D-Channel Busy no skb");
227 cs->writeisac(cs, IPACX_CMDRD, 0x01); // Tx reset, generates XPR
236 dch_empty_fifo(struct IsdnCardState *cs, int count)
240 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
241 debugl1(cs, "dch_empty_fifo()");
244 if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
245 if (cs->debug & L1_DEB_WARN)
246 debugl1(cs, "dch_empty_fifo() incoming message too large");
247 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
248 cs->rcvidx = 0;
252 ptr = cs->rcvbuf + cs->rcvidx;
253 cs->rcvidx += count;
255 cs->readisacfifo(cs, ptr, count);
256 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
258 if (cs->debug & L1_DEB_ISAC_FIFO) {
259 char *t = cs->dlog;
263 debugl1(cs, "%s", cs->dlog);
271 dch_fill_fifo(struct IsdnCardState *cs)
276 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
277 debugl1(cs, "dch_fill_fifo()");
279 if (!cs->tx_skb) return;
280 count = cs->tx_skb->len;
290 ptr = cs->tx_skb->data;
291 skb_pull(cs->tx_skb, count);
292 cs->tx_cnt += count;
293 cs->writeisacfifo(cs, ptr, count);
294 cs->writeisac(cs, IPACX_CMDRD, cmd);
297 if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
298 debugl1(cs, "dch_fill_fifo dbusytimer running");
299 del_timer(&cs->dbusytimer);
301 init_timer(&cs->dbusytimer);
302 cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
303 add_timer(&cs->dbusytimer);
305 if (cs->debug & L1_DEB_ISAC_FIFO) {
306 char *t = cs->dlog;
310 debugl1(cs, "%s", cs->dlog);
318 dch_int(struct IsdnCardState *cs)
324 istad = cs->readisac(cs, IPACX_ISTAD);
330 rstad = cs->readisac(cs, IPACX_RSTAD);
333 if (cs->debug & L1_DEB_WARN)
334 debugl1(cs, "dch_int(): invalid frame");
336 if (cs->debug & L1_DEB_WARN)
337 debugl1(cs, "dch_int(): RDO");
339 if (cs->debug & L1_DEB_WARN)
340 debugl1(cs, "dch_int(): CRC error");
341 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
343 count = cs->readisac(cs, IPACX_RBCLD);
347 dch_empty_fifo(cs, count);
348 if ((count = cs->rcvidx) > 0) {
349 cs->rcvidx = 0;
353 memcpy(skb_put(skb, count), cs->rcvbuf, count);
354 skb_queue_tail(&cs->rq, skb);
358 cs->rcvidx = 0;
359 schedule_event(cs, D_RCVBUFREADY);
363 dch_empty_fifo(cs, D_FIFO_SIZE);
367 if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_int(): RFO");
368 cs->writeisac(cs, IPACX_CMDRD, 0x40); //RRES
372 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
373 del_timer(&cs->dbusytimer);
374 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
375 schedule_event(cs, D_CLEARBUSY);
376 if (cs->tx_skb) {
377 if (cs->tx_skb->len) {
378 dch_fill_fifo(cs);
382 dev_kfree_skb_irq(cs->tx_skb);
383 cs->tx_skb = NULL;
384 cs->tx_cnt = 0;
387 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
388 cs->tx_cnt = 0;
389 dch_fill_fifo(cs);
392 schedule_event(cs, D_XMTBUFREADY);
398 if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_int(): XDU");
399 if (cs->tx_skb) {
400 skb_push(cs->tx_skb, cs->tx_cnt); // retransmit
401 cs->tx_cnt = 0;
402 dch_fill_fifo(cs);
405 debugl1(cs, "ISAC XDU no skb");
413 dch_setstack(struct PStack *st, struct IsdnCardState *cs)
421 dch_init(struct IsdnCardState *cs)
425 cs->setstack_d = dch_setstack;
427 cs->dbusytimer.function = (void *) dbusy_timer_handler;
428 cs->dbusytimer.data = (long) cs;
429 init_timer(&cs->dbusytimer);
431 cs->writeisac(cs, IPACX_TR_CONF0, 0x00); // clear LDD
432 cs->writeisac(cs, IPACX_TR_CONF2, 0x00); // enable transmitter
433 cs->writeisac(cs, IPACX_MODED, 0xC9); // transparent mode 0, RAC, stop/go
434 cs->writeisac(cs, IPACX_MON_CR, 0x00); // disable monitor channel
454 spin_lock_irqsave(&bcs->cs->lock, flags);
463 spin_unlock_irqrestore(&bcs->cs->lock, flags);
466 spin_lock_irqsave(&bcs->cs->lock, flags);
475 spin_unlock_irqrestore(&bcs->cs->lock, flags);
485 spin_lock_irqsave(&bcs->cs->lock, flags);
488 spin_unlock_irqrestore(&bcs->cs->lock, flags);
495 spin_lock_irqsave(&bcs->cs->lock, flags);
499 spin_unlock_irqrestore(&bcs->cs->lock, flags);
512 struct IsdnCardState *cs;
515 cs = bcs->cs;
517 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
518 debugl1(cs, "bch_empty_fifo()");
522 if (cs->debug & L1_DEB_WARN)
523 debugl1(cs, "bch_empty_fifo() incoming packet too large");
524 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
531 while (cnt--) *ptr++ = cs->BC_Read_Reg(cs, hscx, IPACX_RFIFOB);
532 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
537 if (cs->debug & L1_DEB_HSCX_FIFO) {
542 debugl1(cs, "%s", bcs->blog);
552 struct IsdnCardState *cs;
556 cs = bcs->cs;
557 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
558 debugl1(cs, "bch_fill_fifo()");
577 while (cnt--) cs->BC_Write_Reg(cs, hscx, IPACX_XFIFOB, *p++);
578 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, (more ? 0x08 : 0x0a));
580 if (cs->debug & L1_DEB_HSCX_FIFO) {
585 debugl1(cs, "%s", bcs->blog);
593 bch_int(struct IsdnCardState *cs, u_char hscx)
601 bcs = cs->bcs + hscx;
602 istab = cs->BC_Read_Reg(cs, hscx, IPACX_ISTAB);
609 rstab = cs->BC_Read_Reg(cs, hscx, IPACX_RSTAB);
612 if (cs->debug & L1_DEB_WARN)
613 debugl1(cs, "bch_int() B-%d: invalid frame", hscx);
615 if (cs->debug & L1_DEB_WARN)
616 debugl1(cs, "bch_int() B-%d: RDO mode=%d", hscx, bcs->mode);
618 if (cs->debug & L1_DEB_WARN)
619 debugl1(cs, "bch_int() B-%d: CRC error", hscx);
620 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
623 count = cs->BC_Read_Reg(cs, hscx, IPACX_RBCLB) & (B_FIFO_SIZE - 1);
627 if (cs->debug & L1_DEB_HSCX_FIFO)
628 debugl1(cs, "bch_int Frame %d", count);
658 if (cs->debug & L1_DEB_WARN)
659 debugl1(cs, "bch_int() B-%d: RFO error", hscx);
660 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x40); // RRES
703 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x01); // XRES
704 if (cs->debug & L1_DEB_WARN)
705 debugl1(cs, "bch_int() B-%d XDU error", hscx);
715 struct IsdnCardState *cs = bcs->cs;
719 if (cs->debug & L1_DEB_HSCX)
720 debugl1(cs, "mode_bch() switch B-%d mode %d chan %d", hscx, mode, bc);
727 cs->writeisac(cs, IPACX_BCHA_TSDP_BC1, 0x80 | bc);
728 cs->writeisac(cs, IPACX_BCHA_CR, 0x88);
732 cs->writeisac(cs, IPACX_BCHB_TSDP_BC1, 0x80 | bc);
733 cs->writeisac(cs, IPACX_BCHB_CR, 0x88);
738 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC0); // rec off
739 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x30); // std adj.
740 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, 0xFF); // ints off
741 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
744 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0x88); // ext transp mode
745 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x00); // xxx00000
746 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
747 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK);
750 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC8); // transp mode 0
751 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x01); // idle=hdlc flags crc enabled
752 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
753 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK);
782 bch_open_state(struct IsdnCardState *cs, struct BCState *bcs)
828 bch_init(struct IsdnCardState *cs, int hscx)
830 cs->bcs[hscx].BC_SetStack = bch_setstack;
831 cs->bcs[hscx].BC_Close = bch_close_state;
832 cs->bcs[hscx].hw.hscx.hscx = hscx;
833 cs->bcs[hscx].cs = cs;
834 bch_mode(cs->bcs + hscx, 0, hscx);
846 interrupt_ipacx(struct IsdnCardState *cs)
850 while ((ista = cs->readisac(cs, IPACX_ISTA))) {
854 if (ista & 0x80) bch_int(cs, 0); // B channel interrupts
855 if (ista & 0x40) bch_int(cs, 1);
857 if (ista & 0x01) dch_int(cs); // D channel
858 if (ista & 0x10) cic_int(cs); // Layer 1 state
866 clear_pending_ints(struct IsdnCardState *cs)
871 cs->writeisac(cs, IPACX_MASK, 0xff);
872 cs->writeisac(cs, IPACX_MASKD, 0xff);
873 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, 0xff);
874 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, 0xff);
876 ista = cs->readisac(cs, IPACX_ISTA);
877 if (ista & 0x80) cs->BC_Read_Reg(cs, 0, IPACX_ISTAB);
878 if (ista & 0x40) cs->BC_Read_Reg(cs, 1, IPACX_ISTAB);
879 if (ista & 0x10) cs->readisac(cs, IPACX_CIR0);
880 if (ista & 0x01) cs->readisac(cs, IPACX_ISTAD);
888 init_ipacx(struct IsdnCardState *cs, int part)
894 clear_pending_ints(cs);
895 bch_init(cs, 0);
896 bch_init(cs, 1);
897 dch_init(cs);
900 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, _MASKB_IMASK);
901 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, _MASKB_IMASK);
902 cs->writeisac(cs, IPACX_MASKD, _MASKD_IMASK);
903 cs->writeisac(cs, IPACX_MASK, _MASK_IMASK); // global mask register
906 cs->writeisac(cs, IPACX_CMDRD, 0x41);
907 cs->BC_Write_Reg(cs, 0, IPACX_CMDRB, 0x41);
908 cs->BC_Write_Reg(cs, 1, IPACX_CMDRB, 0x41);
909 ph_command(cs, IPACX_CMD_RES);